Datasheet

78
8197C–AVR–05/11
ATtiny261A/461A/861A
11.7.4 8-bit Input Capture Mode
The Timer/Counter0 can also be used in an 8-bit Input Capture mode, see Table 11-3 on page
76 for bit settings. For full description, see the section “Input Capture Unit” on page 74.
11.7.5 16-bit Input Capture Mode
The Timer/Counter0 can also be used in a 16-bit Input Capture mode, see Table 11-3 on page
76 for bit settings. For full description, see the section “Input Capture Unit” on page 74.
11.8 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T0
) is therefore shown as a
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set. Figure 11-7 contains timing data for basic Timer/Counter operation. The figure
shows the count sequence close to the MAX value.
Figure 11-7. Timer/Counter Timing Diagram, no Prescaling
Figure 11-8 shows the same timing data, but with the prescaler enabled.
Figure 11-8. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
Figure 11-9 on page 79 shows the setting of OCF0A and OCF0B in Normal mode.
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)