Datasheet

72
8197C–AVR–05/11
ATtiny261A/461A/861A
Figure 11-2. Prescaler for Timer/Counter0
Note: 1. The synchronization logic on the input pins (T0) is shown in Figure 11-3.
The prescaled clock has a frequency of f
CLK_I/O
/8, f
CLK_I/O
/64, f
CLK_I/O
/256, or f
CLK_I/O
/1024. See
Table 11-4 on page 84 for details.
11.3.1.1 Prescaler Reset
The prescaler is free running, i.e. it operates independently of the Clock Select logic of the
Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the state
of the prescaler will have implications for situations where a prescaled clock is used. One exam-
ple of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 >
CSn[2:0] > 1). The number of system clock cycles from when the timer is enabled to the first
count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8,
64, 256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter
to program execution.
11.3.2 External Clock Source
An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk
T0
). The
T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
Figure 11-3 shows a functional
equivalent block diagram of the T0 synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (
clk
I/O
). The latch is transparent in the
high period of the internal system clock.
The edge detector generates one clk
T
0
pulse for each positive (CSn[2:0] = 7) or negative
(CSn[2:0] = 6) edge it detects. See Table 11-4 on page 84 for details.
PSR0
Clear
clk
T0
T0
clk
I/O
Synchronization