Datasheet

70
8197C–AVR–05/11
ATtiny261A/461A/861A
11. Timer/Counter0
11.1 Features
• Clear Timer on Compare Match (Auto Reload)
• One Input Capture unit
• Four Independent Interrupt Sources (TOV0, OCF0A, OCF0B, ICF0)
• 8-bit Mode with Two Independent Output Compare Units
• 16-bit Mode with One Independent Output Compare Unit
11.2 Overview
Timer/Counter0 is a general purpose 8/16-bit Timer/Counter module, with two/one Output Com-
pare units and Input Capture feature.
The general operation of Timer/Counter0 is described in 8/16-bit mode. A simplified block dia-
gram of the 8/16-bit Timer/Counter is shown in Figure 11-1. CPU accessible I/O Registers,
including I/O bits and I/O pins, are shown in bold. For actual placement of I/O pins, refer to “Pin-
out ATtiny261A/461A/861A” on page 2. Device-specific I/O Register and bit locations are listed
in the “Register Description” on page 83.
Figure 11-1. 8-/16-bit Timer/Counter Block Diagram
11.2.1 Registers
The Timer/Counter0 Low Byte Register (TCNT0L) and Output Compare Registers (OCR0A and
OCR0B) are 8-bit registers. Interrupt request (abbreviated Int.Req. in Figure 11-1) signals are all
Clock Select
Timer/Counter
DATA BUS
OCRnB
=
TCNTnL
Noise
Canceler
ICPn
=
Edge
Detector
Control Logic
TOP
Count
Clear
Direction
TOVn (Int. Req.)
OCnA (Int. Req.)
OCnB (Int. Req.)
ICFn (Int. Req.)
TCCRnA TCCRnB
( From Analog
Comparator Ouput )
Tn
Edge
Detector
( From Prescaler )
clk
Tn
=
OCRnA
TCNTnH
Fixed TOP value