Datasheet

68
8197C–AVR–05/11
ATtiny261A/461A/861A
Note: 1. INTRC means that one of the internal oscillators is selected (by the CKSEL fuses), EXTCK
means that external clock is selected (by the CKSEL fuses).
10.3 Register Description
10.3.1 MCUCR – MCU Control Register
• Bit 6 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-
figuring the Pin” on page 55 for more details about this feature.
10.3.2 PORTA – Port A Data Register
10.3.3 DDRA – Port A Data Direction Register
Table 10-8. Overriding Signals for Alternate Functions in PB[3:0]
Signal
Name
PB3/OC1B/
PCINT11
PB2/SCK/USCK/SCL/O
C1B/PCINT10
PB1/MISO/DO/OC1A/
PCINT9
PB0/MOSI/DI/SDA/
OC1A/PCINT8
PUOE 0 0 0 0
PUOV 0 0 0 0
DDOE 0
USI_TWO_WIRE •
USIPOS
0
USI_TWO_WIRE •
USIPOS
DDOV 0
(USI_SCL_HOLD +
PORTB2) • DDB2 •
USIPOS
0
(SDA
+ PORTB0) •
DDB0 • USIPOS
PVOE OC1B Enable
OC1B Enable
+ USIPOS
• USI_TWO_WIRE •
DDB2
OC1A Enable +
USIPOS
•
USI_THREE_WIRE
OC1A Enable
+
(USI_TWO_WIRE •
DDB0 • USIPOS
)
PVOV OC1B OC1B
OC1A + (DO •
USIPOS
)
OC1A
PTOE 0 USITC • USIPOS
00
DIEOE PCINT11 • PCIE
PCINT10 • PCIE +
USISIE • USIPOS
PCINT9 • PCIE
PCINT8 • PCIE +
(USISIE • USIPOS
)
DIEOV 0 0 0 0
DI PCINT11 USCK/SCL/PCINT10 PCINT9 DI/SDA/PCINT8
AIO
Bit 7 6 5 4 3 2 1 0
0x35 (0x55)
BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 MCUCR
Read/Write R/W R/W R/W R/W R/W R/W R R
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x1B (0x3B) PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x1A (0x3A) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000