Datasheet

53
8197C–AVR–05/11
ATtiny261A/461A/861A
• Bit 5 – PCIF: Pin Change Interrupt Flag
When a logic change on any PCINT15 pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bits 4:0 – Res: Reserved Bits
These bits are reserved and will always read as zero.
9.3.4 PCMSK0 – Pin Change Mask Register A
• Bits 7:0 – PCINT[7:0]: Pin Change Enable Mask 7:0
Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[7:0] is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
9.3.5 PCMSK1 – Pin Change Mask Register B
• Bits 7:0 – PCINT[15:8]: Pin Change Enable Mask 15:8
Each PCINT[15:8] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[11:8] is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin, and if PCINT[15:12] is set and the PCIE1 bit in GIMSK is set, pin
change interrupt is enabled on the corresponding I/O pin. If PCINT[15:8] is cleared, pin change
interrupt on the corresponding I/O pin is disabled.
Bit 76543210
0x23 (0x43) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0
Read/Write R/W R/W R/W R/w R/W R/W R/W R/W
Initial Value11001000
Bit 76543210
0x22 (0x42) PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1
Read/Write R/W R/W R/W R/w R/W R/W R/W R/W
Initial Value11111111