Datasheet

8197C–AVR–05/11

ATtiny261A/461A/861A

Address Labels Code Comments

0x0000 rjmp RESET ; Reset Handler

0x0001 rjmp EXT_INT0 ; IRQ0 Handler

0x0002 rjmp PCINT ; PCINT Handler

0x0003 rjmp TIM1_COMPA ; Timer1 CompareA Handler

0x0004 rjmp TIM1_COMPB ; Timer1 CompareB Handler

0x0005 rjmp TIM1_OVF ; Timer1 Overflow Handler

0x0006 rjmp TIM0_OVF ; Timer0 Overflow Handler

0x0007 rjmp USI_START ; USI Start Handler

0x0008 rjmp USI_OVF ; USI Overflow Handler

0x0009 rjmp EE_RDY ; EEPROM Ready Handler

0x000A rjmp ANA_COMP ; Analog Comparator Handler

0x000B rjmp ADC_ISR ; ADC Conversion Handler

0x000C rjmp WDT ; WDT Interrupt Handler

0x000D rjmp EXT_INT1 ; IRQ1 Handler

0x000E rjmp TIM0_COMPA ; Timer0 CompareA Handler

0x000F rjmp TIM0_COMPB ; Timer0 CompareB Handler

0x0010 rjmp TIM0_CAPT ; Timer0 Capture Event Handler

0x0011 rjmp TIM1_COMPD ; Timer1 CompareD Handler

0x0012 rjmp FAULT_PROTECTION ; Timer1 Fault Protection

0x0013 RESET: ldi r16, low(RAMEND) ; Main program start

0x0014 ldi r17, high(RAMEND); Tiny861 have also SPH

0x0015 out SPL, r16 ; Set Stack Pointer to top of RAM

0x0016 out SPH, r17 ; Tiny861 have also SPH

0x0017 sei ; Enable interrupts

0x0018 <instr>

... ...

9.2 External Interrupts

The External Interrupts are triggered by the INT0 or INT1 pin or any of the PCINT[15:0] pins.

Observe that, if enabled, the interrupts will trigger even if the INT0, INT1 or PCINT[15:0] pins are

configured as outputs. This feature provides a way of generating a software interrupt. Pin

change interrupts PCI will trigger if any enabled PCINT[15:0] pin toggles. The PCMSK Register

control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT[15:0]

are detected asynchronously. This implies that these interrupts can be used for waking the part

also from sleep modes other than Idle mode.

The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is

set up as indicated in the specification for the MCU Control Register – MCUCR. When the INT0

interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the

pin is held low. Note that recognition of falling or rising edge interrupts on INT0 or INT1 requires

the presence of an I/O clock, described in “Clock Subsystems” on page 24.