Datasheet

39
8197C–AVR–05/11
ATtiny261A/461A/861A
• Bits 4:3 – SM[1:0]: Sleep Mode Select Bits 1 and 0
These bits select between the four available sleep modes as shown in Table 7-2.
• Bit 2 – BODSE: BOD Sleep Enable
The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD
disable is controlled by a timed sequence.
7.5.2 PRR – Power Reduction Register
The Power Reduction Register provides a method to reduce power consumption by allowing
peripheral clock signals to be disabled.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 3 – PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1
is enabled, operation will continue like before the shutdown.
• Bit 2 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0
is enabled, operation will continue like before the shutdown.
• Bit 1 – PRUSI: Power Reduction USI
Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When
waking up the USI again, the USI should be re initialized to ensure proper operation.
• Bit 0 – PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.
Also analog comparator needs this clock.
Table 7-2. Sleep Mode Select
SM1 SM0 Sleep Mode
00Idle
0 1 ADC Noise Reduction
1 0 Power-down
1 1 Standby
Bit 76543 210
0x36 (0x56) – – – – PRTIM1 PRTIM0 PRUSI PRADC PRR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0