Datasheet

195
8197C–AVR–05/11
ATtiny261A/461A/861A
Figure 19-6. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note: The timing requirements shown in Figure 19-5 (i.e., t
DVXH
, t
XHXL
, and t
XLDX
) also apply to loading operation.
Figure 19-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements
Note: The timing requirements shown in Figure 19-5 (i.e., t
DVXH
, t
XHXL
, and t
XLDX
) also apply to reading operation.
XTAL1
XLXH
t
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
DATA
PAGEL/BS1
XA0
XA1/BS2
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
XTAL1
OE
ADDR0 (Low Byte) DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
DATA
PAGEL/BS1
XA0
XA1/BS2
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
t
BVDV
t
OLDV
t
XLOL
t
OHDZ
Table 19-12. Parallel Programming Characteristics, V
CC
= 5V ± 10%
Symbol Parameter Min Typ Max Units
V
PP
Programming Enable Voltage 11.5 12.5 V
I
PP
Programming Enable Current 250 µA
t
DVXH
Data and Control Valid before XTAL1 High 67 ns