Datasheet

159
8197C–AVR–05/11
ATtiny261A/461A/861A
If these bits are changed during a conversion, the change will not go into effect until this conver-
sion is complete (ADIF in ADCSRA is set).
15.13.4 ADCSRB – ADC Control and Status Register B
• Bit 7 – BIN: Bipolar Input Mode
The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected
by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided conversions
are supported and the voltage on the positive input must always be larger than the voltage on
the negative input. Otherwise the result is saturated to the voltage reference. In the bipolar mode
two-sided conversions are supported and the result is represented in the two’s complement
form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits +
1 sign bit.
• Bit 6 – GSEL: Gain Select
The Gain Select bit selects the 32x gain instead of the 20x gain and the 8x gain instead of the 1x
gain when the Gain Select bit is written to one.
• Bit 5 – Res: Reserved Bit
This bit is reserved and will always read zero.
• Bit 4 – REFS2: Reference Selection Bit
These bit selects either the voltage reference of 1.1 V or 2.56 V for the ADC, as shown in Table
15-4. If active channels are used, using AVCC or an external AREF higher than (AVCC - 1V) is
not recommended, as this will affect ADC accuracy.
• Bit 3 – MUX5: Analog Channel and Gain Selection Bit 5
The MUX5 bit is the MSB of the Analog Channel and Gain Selection bits. Refer to Table 15-5 for
details. If this bit is changed during a conversion, the change will not go into effect until this
conversion is complete (ADIF in ADCSRA is set).
• Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conver-
sion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a
trigger source that is cleared to a trigger source that is set, will generate a positive edge on the
Bit 76543210
0x03 (0x23) BIN GSEL – REFS2 MUX5 ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0