Datasheet

134
8197C–AVR–05/11
ATtiny261A/461A/861A
Note: 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively
to avoid confusion between the modes of operation.
• Bits 3:2 – USICS[1:0]: Clock Source Select
These bits set the clock source for the USI Data Registerr and counter. The data output latch
ensures that the output is changed at the opposite edge of the sampling of the data input
(DI/SDA) when using external clock source (USCK/SCL). When software strobe or
Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and
therefore the output is changed immediately. Clearing the USICS[1:0] bits enables software
strobe option. When using this option, writing a one to the USICLK bit clocks both the USI Data
Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is no longer
used as a strobe, but selects between external clocking and software clocking by the USITC
strobe bit.
Table 13-2 on page 134 shows the relationship between the USICS[1:0] and USICLK setting
and clock source used for the USI Data Register and the 4-bit counter.
10
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins
(1)
.
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and
use open-collector output drives. The output drivers are enabled by setting the
corresponding bit for SDA and SCL in the DDRA register.
When the output driver is enabled for the SDA pin, the output driver will force the
line SDA low if the output of the
USI Data Register or the corresponding bit in
the PORTA register is zero. Otherwise, the SDA line will not be driven (i.e., it is
released). When the SCL pin output driver is enabled the SCL line will be forced
low if the corresponding bit in the PORTA register is zero, or by the start
detector. Otherwise the SCL line will not be driven.
The SCL line is held low when a start detector detects a start condition and the
output is enabled. Clearing the Start Condition Flag (USISIF) releases the line.
The SDA and SCL pin inputs is not affected by enabling this mode. Pull-ups on
the SDA and SCL port pin are disabled in Two-wire mode.
11
Two-wire mode. Uses SDA and SCL pins.
Same operation as in two-wire mode above, except that the SCL line is also
held low when a counter overflow occurs, and until the Counter Overflow Flag
(USIOIF) is cleared.
Table 13-2. Relations between the USICS[1:0] and USICLK Setting
USICS1 USICS0 USICLK
USI Data Register Clock
Source 4-bit Counter Clock Source
0 0 0 No Clock No Clock
001
Software clock strobe
(USICLK)
Software clock strobe
(USICLK)
01X
Timer/Counter0 Compare
Match
Timer/Counter0 Compare
Match
1 0 0 External, positive edge External, both edges
Table 13-1. Relationship between USIWM[1:0] and USI Operation (Continued)
USIWM1 USIWM0 Description