Datasheet

124
8197C–AVR–05/11
ATtiny261A/461A/861A
13. USI – Universal Serial Interface
13.1 Features
• Two-wire Synchronous Data Transfer (Master or Slave)
• Three-wire Synchronous Data Transfer (Master or Slave)
• Data Received Interrupt
• Wakeup from Idle Mode
• In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
• Two-wire Start Condition Detector with Interrupt Capability
13.2 Overview
The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load.
A simplified block diagram of the USI is shown in Figure 13-1 For actual placement of I/O pins
refer to “Pinout ATtiny261A/461A/861A” on page 2. Device-specific I/O Register and bit loca-
tions are listed in the “Register Descriptions” on page 131.
Figure 13-1. Universal Serial Interface, Block Diagram
The 8-bit USI Data Register (USIDR) is directly accessible via the data bus and contains the
incoming and outgoing data. The register has no buffering so the data must be read as quickly
as possible to ensure that no data is lost. The data register is a serial shift register where the
most significant bit is connected to one of two output pins depending of the wire mode configura-
tion. A transparent latch between the output of the data register and the output pin delays the
change of data output to the opposite clock edge of the data input sampling. The serial input is
always sampled from the Data Input (DI) pin, regardless of the configuration.
DATA BUS
USIPF
USITC
USICLK USICS0 USICS1
USIOIFUSIOIE
USIDC
USISIF
USIWM0 USIWM1
USISIE Bit7
Two-wire Clock
Control Unit
DO
(Output only)
DI/SDA
(Input/Open Drain)
USCK/SCL
(Input/Open Drain)
4-bit Counter
USIDR
USISR
DQ
LE
USICR
CLOCK
HOLD
TIM0 COMP
Bit0
[1]
3
0
1
2
3
0
1
2
0
1
2
USIDB