Datasheet

120
8197C–AVR–05/11
ATtiny261A/461A/861A
12.12.7 TCNT1 – Timer/Counter1
This 8-bit register contains the value of Timer/Counter1.
The Timer/Counter1 is realized as a 10-bit up/down counter with read and write access. Due to
synchronization of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one
and half CPU clock cycles in synchronous mode and at most one CPU clock cycles for asyn-
chronous mode. When a 10-bit accuracy is preferred, special procedures must be followed for
accessing the 10-bit TCNT1 register via the 8-bit AVR data bus. These procedures are
described in section “Accessing 10-Bit Registers” on page 107. Alternatively the Timer/Counter1
can be used as an 8-bit Timer/Counter. Note that the Timer/Counter1 always starts counting up
after writing the TCNT1 register.
12.12.8 TC1H – Timer/Counter1 High Byte
The temporary Timer/Counter1 register is an 2-bit read/write register.
• Bits 7:2 – Res: Reserved Bits
These bits are reserved and always reads zero.
• Bits 1:0 – TC19, TC18: Two MSB bits of the 10-bit accesses
If 10-bit accuracy is used, the Timer/Counter1 High Byte Register (TC1H) is used for temporary
storing the MSB bits (TC19, TC18) of the 10-bit acceses. The same TC1H register is shared
between all 10-bit registers within the Timer/Counter1. Note that special procedures must be fol-
lowed when accessing the 10-bit TCNT1 register via the 8-bit AVR data bus. These procedures
are described in section “Accessing 10-Bit Registers” on page 107.
12.12.9 OCR1A – Timer/Counter1 Output Compare Register A
The output compare register A is an 8-bit read/write register.
The Timer/Counter Output Compare Register A contains data to be continuously compared with
Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does
only occur if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and
OCR1A to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1A after a synchronization delay follow-
ing the compare event.
Note that, if 10-bit accuracy is used special procedures must be followed when accessing the
internal 10-bit Ouput Compare Registers via the 8-bit AVR data bus. These procedures are
described in section “Accessing 10-Bit Registers” on page 107.
Bit 76543210
0x2E (0x4E) MSB LSB TCNT1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
Bit 76543210
0x25 (0x45) ––––––TC19 TC18 TC1H
Read/WriteRRRRRRR/WR/W
Initial value00000000
Bit 76543210
0x2D (0x4D) MSB LSB OCR1A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000