Datasheet

115
8197C–AVR–05/11
ATtiny261A/461A/861A
The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the
Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can
be generated. The Dead Time prescaler is controlled by two bits DTPS11 and DTPS10 from the
Dead Time Prescaler register. These bits define the division factor of the Dead Time prescaler.
The division factors are given in Table 12-16.
• Bits 3:0 – CS1[3:0]: Clock Select Bits 3 - 0
The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.
The Stop condition provides a Timer Enable/Disable function.
Table 12-16. Division factors of the Dead Time prescaler
DTPS11 DTPS10 Prescaler divides the T/C1 clock by
0 0 1x (no division)
012x
104x
118x
Table 12-17. Timer/Counter1 Prescaler Select
CS13 CS12 CS11 CS10 Asynchronous Clocking Mode Synchronous Clocking Mode
0000T/C1 stopped T/C1 stopped
0001PCK CK
0010PCK/2 CK/2
0011PCK/4 CK/4
0100PCK/8 CK/8
0101PCK/16 CK/16
0110PCK/32 CK/32
0111PCK/64 CK/64
1000PCK/128 CK/128
1001PCK/256 CK/256
1010PCK/512 CK/512
1011PCK/1024 CK/1024
1100PCK/2048 CK/2048
1101PCK/4096 CK/4096
1110PCK/8192 CK/8192
1111PCK/16384 CK/16384