Datasheet

105
8197C–AVR–05/11
ATtiny261A/461A/861A
12.9 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T1
) is therefore shown as a
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
Figure 12-15 contains timing data for basic Timer/Counter operation. The figure shows the count
sequence close to the MAX value in all modes other than Phase and Frequency Correct PWM
Mode.
Figure 12-15. Timer/Counter Timing Diagram, no Prescaling
Figure 12-16 shows the same timing data, but with the prescaler enabled, in all modes other
than Phase and Frequency Correct PWM Mode.
Figure 12-16. Timer/Counter Timing Diagram, with Prescaler (f
clkT1
/8)
Figure 12-17 shows the setting of OCF1A, OCF1B and OCF1D in all modes.
Table 12-7. Configuration of Output Compare Pins OC1D and OC1D
in PWM6 Mode
COM1D1 COM1D0 OC1D Pin (PB4) OC1D Pin (PB5)
0 0 Disconnected Disconnected
01OC1A •
OC1OE4 OC1A • OC1OE5
10OC1A • OC1OE4 OC1A • OC1OE5
11OC1A • OC1OE4 OC1A • OC1OE5
clk
Tn
(clk
PCK
/1)
TOVn
clk
PCK
TCNTn TOP - 1 TOP BOTTOM BOTTOM + 1
TOVn
TCNTn
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
PCK
clk
Tn
(clk
PCK
/8)