Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • – 123 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz High Endurance Non-volatile Memory Segments – 2/4/8K Bytes of In-System Self-Programmable Flash Program Memory • Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes of In-System Programmable EEPROM • Endurance: 100,000 Wri
1. Pin Configurations Figure 1-1.
ATtiny261A/461A/861A 1.1 1.1.1 Pin Descriptions VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 AVCC Analog supply voltage. This is the supply voltage pin for the Analog-to-digital Converter (ADC), the analog comparator, the Brown-Out Detector (BOD), the internal voltage reference and Port A. It should be externally connected to VCC, even if some peripherals such as the ADC are not used. If the ADC is used AVCC should be connected to VCC through a low-pass filter. 1.1.4 AGND Analog ground. 1.1.
2. Overview ATtiny261A/461A/861A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the devices achieve throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Block Diagram Watchdog Timer Watchdog Oscillator Oscillator Circuits / Clock Generation VCC GND Figure 2-1.
ATtiny261A/461A/861A The ATtiny261A/461A/861A provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 16 general purpose I/O lines, 32 general purpose working registers, an 8-bit Timer/Counter with compare modes, an 8bit high speed Timer/Counter, a Universal Serial Interface, Internal and External Interrupts, an 11-channel, 10-bit ADC, a programmable Watchdog Timer with internal oscillator, and four software selectable power saving mode
3. General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation.
ATtiny261A/461A/861A 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 Architectural Overview Figure 4-1.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
ATtiny261A/461A/861A 4.3.1 SREG – AVR Status Register Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
4.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATtiny261A/461A/861A 15 Y-register YH YL 7 0 R29 (0x1D) Z-register 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In different addressing modes these address registers function as automatic increment and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing temporary data, local variables and return addresses for interrupts and subroutine calls.
4.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept.
ATtiny261A/461A/861A priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in the following examples. Assembly Code Example sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ Note: 4.7.
ATtiny261A/461A/861A 5. Memories This section describes the different memories of the ATtiny261A/461A/861A. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny261A/461A/861A features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 5.1 In-System Re-programmable Flash Program Memory The ATtiny261A/461A/861A contains 2/4/8K byte On-chip In-System Reprogrammable Flash memory for program storage.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of internal data SRAM in the ATtiny261A/461A/861A are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10. Figure 5-2.
ATtiny261A/461A/861A 5.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 5-1 on page 22. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down.
The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on page 32. 5.3.6 Program Examples The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATtiny261A/461A/861A The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 5.4 I/O Memory The I/O space definition of the ATtiny261A/461A/861A is shown in “Register Summary” on page 277. All I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed using the LD/LDS/LDD and ST/STS/STD instructions, enabling data transfer between the 32 general purpose working registers and the I/O space.
ATtiny261A/461A/861A 5.5.2 EEARL – EEPROM Address Register Bit 7 6 5 4 3 2 1 0 0x1E (0x3E) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X/0 X X X X X X X EEARL • Bit 7 – EEAR7: EEPROM Address This is the most significant EEPROM address bit of ATtiny461A. In devices with less EEPROM, i.e. ATtiny261A, this bit is reserved and will always read zero.
old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 5-1. Table 5-1. EEPROM Mode Bits EEPM1 EEPM0 Programming Time 0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Operation Reserved for future use When EEPE is set, any write to EEPMn will be ignored.
ATtiny261A/461A/861A 5.5.5 GPIOR2 – General Purpose I/O Register 2 Bit 5.5.6 6 5 4 3 2 1 0 MSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 LSB 5 4 3 2 1 GPIOR2 GPIOR1 – General Purpose I/O Register 1 Bit 5.5.
6. Clock System Figure 6-1 presents the principal clock systems and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 35. Figure 6-1.
ATtiny261A/461A/861A 6.1.3 Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 6.1.4 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 6.1.
mencing normal operation. The watchdog oscillator is used for timing this real-time part of the start-up time. The number of WD oscillator cycles used for each time-out is shown in Table 6-2. Table 6-2. 6.2.1 Number of Watchdog Oscillator Cycles Typ Time-out Number of Cycles 4 ms 512 64 ms 8K (8,192) External Clock To drive the device from an external clock source, CLKI should be driven as shown in Figure 62. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
ATtiny261A/461A/861A The fast peripheral clock, clkPCK, can be selected as the clock source for Timer/Counter1 and a prescaled version of the PLL output, clkPLL, can be selected as system clock. See Figure 6-3 for a detailed illustration on the PLL clock system. Figure 6-3.
When the PLL output is selected as clock source, the start-up times are determined by SUT fuse bits as shown in Table 6-5. Table 6-5. 6.2.3 Start-up Times for the PLLCK SUT[1:0] Start-up Time from Power Down Additional Delay from Power-On-Reset (VCC = 5.
ATtiny261A/461A/861A It is possible to reach a higher accuracy than factory calibration by changing the OSCCAL register from software. See “OSCCAL – Oscillator Calibration Register” on page 32. The accuracy of this calibration is shown as User calibration in Table 19-2 on page 187. When this oscillator is used as device clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out.
6.2.6 Crystal Oscillator / Ceramic Resonator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 6-4. Either a quartz crystal or a ceramic resonator may be used. Figure 6-4. Crystal Oscillator Connections C2 C1 XTAL2 XTAL1 GND C1 and C2 should always be equal for both crystals and resonators.
ATtiny261A/461A/861A Table 6-12.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting. 6.4 Clock Output Buffer The device can output the system clock on the CLKO pin (when not used as XTAL2 pin). To enable the output, the CKOUT Fuse has to be programmed.
ATtiny261A/461A/861A • Bits 6:4 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.
Table 6-13.
ATtiny261A/461A/861A 7. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.1.
ATtiny261A/461A/861A 7.3 Power Reduction Register The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 39, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock.
7.4.5 Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Watchdog Timer” on page 43 for details on how to configure the Watchdog Timer. 7.4.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power.
ATtiny261A/461A/861A • Bits 4:3 – SM[1:0]: Sleep Mode Select Bits 1 and 0 These bits select between the four available sleep modes as shown in Table 7-2. Table 7-2. Sleep Mode Select SM1 SM0 Sleep Mode 0 0 Idle 0 1 ADC Noise Reduction 1 0 Power-down 1 1 Standby • Bit 2 – BODSE: BOD Sleep Enable The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD disable is controlled by a timed sequence. 7.5.
8. System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 8-1 shows the reset logic.
ATtiny261A/461A/861A 8.2 Reset Sources The ATtiny261A/461A/861A has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. • Brown-out Reset.
8.2.2 External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see “System and Reset Characteristics” on page 188) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after the Time-out period – tTOUT – has expired. Figure 8-4.
ATtiny261A/461A/861A 8.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to “Watchdog Timer” on page 43 for details on operation of the Watchdog Timer. Figure 8-6. Watchdog Reset During Operation CC CK 8.3 Internal Voltage Reference ATtiny261A/461A/861A features an internal bandgap reference.
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down. To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in Table 8-1 Refer to “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 44 for details. Table 8-1.
ATtiny261A/461A/861A 1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. 8.4.2 Code Examples The following code example shows one assembly and one C function for turning off the WDT.
8.5 8.5.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 7 6 5 4 3 2 1 0 0x34 (0x54) – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs.
ATtiny261A/461A/861A the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 8-2. Watchdog Timer Configuration WDE WDIE Watchdog Timer State Action on Time-out 0 0 Stopped None 0 1 Running Interrupt 1 0 Running Reset 1 1 Running Interrupt • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled.
• Bits 5, 2:0 – WDP[3:0]: Watchdog Timer Prescaler 3 - 0 The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 8-3. Table 8-3. WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K (2048) cycles 16 ms 0 0 0 1 4K (4096) cycles 32 ms 0 0 1 0 8K (8192) cycles 64 ms 0 0 1 1 16K (16384) cycles 0.
ATtiny261A/461A/861A 9. Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny261A/461A/861A. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. 9.1 Interrupt Vectors Interrupt vectors of ATtiny261A/461A/861A are described in Table 9-1 below. Table 9-1. Reset and Interrupt Vectors Vector No.
Address Labels Code 9.
ATtiny261A/461A/861A 9.2.1 Low Level Interrupt A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in all sleep modes except Idle). Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt.
Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector.
ATtiny261A/461A/861A • Bit 5 – PCIF: Pin Change Interrupt Flag When a logic change on any PCINT15 pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. • Bits 4:0 – Res: Reserved Bits These bits are reserved and will always read as zero. 9.3.
10. I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability.
ATtiny261A/461A/861A 10.1 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx WPx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 10.1.
be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 10.1.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
ATtiny261A/461A/861A Figure 10-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
10.1.5 Digital Input Enable and Sleep Modes As shown in Figure 10-2, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins.
ATtiny261A/461A/861A C Code Example unsigned char i; ... /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<
Figure 10-5.
ATtiny261A/461A/861A Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 10-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
10.2.1 Alternate Functions of Port A The Port A pins with alternate function are shown in Table 10-3. Table 10-3.
ATtiny261A/461A/861A • Port A, Bit 5 – ADC4/AIN2/PCINT5 • ADC4: Analog to Digital Converter, Channel 4. • AIN2: Analog Comparator Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. • PCINT5: Pin Change Interrupt source 5. • Port A, Bit 4 – ADC3/ICP0/PCINT4 • ADC3: Analog to Digital Converter, Channel 3. • ICP0: Timer/Counter0 Input Capture Pin. • PCINT4: Pin Change Interrupt source 4.
Table 10-4 and Table 10-5 relate the alternate functions of Port A to the overriding signals shown in Figure 10-5 on page 60. Table 10-4.
ATtiny261A/461A/861A 10.2.2 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10-6. Table 10-6.
• ADC10: ADC input Channel 10. Note that ADC input channel 10 uses analog power. • PCINT15: Pin Change Interrupt source 15. • Port B, Bit 6 – ADC9/T0/INT0/PCINT14 • ADC9: ADC input Channel 9. Note that ADC input channel 9 uses analog power. • T0: Timer/Counter0 counter source. • INT0: The PB6 pin can serve as an External Interrupt source 0. • PCINT14: Pin Change Interrupt source 14. • Port B, Bit 5 – XTAL2/CLKO/ADC8/PCINT13 • XTAL2: Chip clock Oscillator pin 2.
ATtiny261A/461A/861A • Port B, Bit 1 – MISO/DO/OC1A/PCINT9 • DO: Three-wire mode Universal Serial Interface Data output. Three-wire mode Data output overrides PORTB1 value and it is driven to the port when data direction bit DDB1 is set (one). PORTB1 still enables the pull-up, if the direction is input and PORTB1 is set (one). • OC1A: Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter1 Compare Match B when configured as an output (DDB1 set).
Table 10-8.
ATtiny261A/461A/861A 10.3.4 PINA – Port A Input Pins Address Bit 10.3.5 7 6 5 4 3 2 1 0 0x19 (0x39) PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A PORTB – Port B Data Register Bit 10.3.
11. Timer/Counter0 11.1 Features • • • • • 11.2 Clear Timer on Compare Match (Auto Reload) One Input Capture unit Four Independent Interrupt Sources (TOV0, OCF0A, OCF0B, ICF0) 8-bit Mode with Two Independent Output Compare Units 16-bit Mode with One Independent Output Compare Unit Overview Timer/Counter0 is a general purpose 8/16-bit Timer/Counter module, with two/one Output Compare units and Input Capture feature. The general operation of Timer/Counter0 is described in 8/16-bit mode.
ATtiny261A/461A/861A visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure. In 16-bit mode one more 8-bit register is available, the Timer/Counter0 High Byte Register (TCNT0H).
Figure 11-2. Prescaler for Timer/Counter0 clk I/O Clear PSR0 T0 Synchronization clkT0 Note: 1. The synchronization logic on the input pins (T0) is shown in Figure 11-3. The prescaled clock has a frequency of fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. See Table 11-4 on page 84 for details. 11.3.1.1 11.3.2 Prescaler Reset The prescaler is free running, i.e. it operates independently of the Clock Select logic of the Timer/Counter.
ATtiny261A/461A/861A Figure 11-3. T0 Pin Sampling D Tn Q D Q D Tn_sync (To Clock Select Logic) Q LE clk I/O Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
internal clock source, selected by the Clock Select bits (CS0[2:0]). When no clock source is selected (CS0[2:0] = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The Timer/Counter Overflow Flag (TOV0) is set when the counter reaches the maximum value and it can be used for generating a CPU interrupt. 11.
ATtiny261A/461A/861A the same system clock as the TCNT0 value is copied into Input Capture Register. If enabled (TICIE0 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF0 flag is automatically cleared when the interrupt is executed. Alternatively the ICF0 flag can be cleared by software by writing a logical one to its I/O bit location. 11.5.1 Input Capture Trigger Source The default trigger source for the Input Capture unit is the Input Capture pin (ICP0).
OCF0B, but in 16-bit mode the match can set only the Output Compare Flag OCF0A as there is only one Output Compare Unit. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. Figure 11-5 shows a block diagram of the Output Compare unit. Figure 11-5.
ATtiny261A/461A/861A The Overflow Flag (TOV0) is set in the same timer clock cycle as when TCNT0L becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal 8-bit mode, a new counter value can be written anytime.
11.7.4 8-bit Input Capture Mode The Timer/Counter0 can also be used in an 8-bit Input Capture mode, see Table 11-3 on page 76 for bit settings. For full description, see the section “Input Capture Unit” on page 74. 11.7.5 16-bit Input Capture Mode The Timer/Counter0 can also be used in a 16-bit Input Capture mode, see Table 11-3 on page 76 for bit settings. For full description, see the section “Input Capture Unit” on page 74. 11.
ATtiny261A/461A/861A Figure 11-9. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 11-10 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 11-10. Timer/Counter Timing Diagram, CTC mode, with Prescaler (fclk_I/O/8) clkPCK clkTn (clkPCK /8) TCNTn (CTC) TOP - 1 OCRnx TOP BOTTOM BOTTOM + 1 TOP OCFnx 11.
The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR0A/B registers. Assembly Code Example ... ; Set TCNT0 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT0H,r17 out TCNT0L,r16 ; Read TCNT0 into r17:r16 in r16,TCNT0L in r17,TCNT0H ... C Code Example unsigned int i; ...
ATtiny261A/461A/861A The following code examples show how to do an atomic read of the TCNT0 register contents. Reading any of the OCR0 register can be done by using the same principle.
The following code examples show how to do an atomic write of the TCNT0H/L register contents. Writing any of the OCR0A/B registers can be done by using the same principle.
ATtiny261A/461A/861A 11.10 Register Description 11.10.1 TCCR0A – Timer/Counter0 Control Register A Bit 7 6 5 4 3 2 1 0 0x15 (0x35) TCW0 ICEN0 ICNC0 ICES0 ACIC0 – – CTC0 Read/Write R/W R/W R/W R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bit 7 – TCW0: Timer/Counter0 Width When this bit is written to one 16-bit mode is selected as described Figure 11-7 on page 78.
11.10.2 TCCR0B – Timer/Counter0 Control Register B Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – TSM PSR0 CS02 CS01 CS01 Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 4 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR0 bit is kept, hence keeping the Prescaler Reset signal asserted.
ATtiny261A/461A/861A 11.10.4 TCNT0H – Timer/Counter0 Register High Byte Bit 7 6 5 0x14 (0x34) 4 3 2 1 0 TCNT0H[7:0] TCNT0H Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 When 16-bit mode is selected (the TCW0 bit is set to one) the Timer/Counter Register TCNT0H combined to the Timer/Counter Register TCNT0L gives direct access, both for read and write operations, to the Timer/Counter unit 16-bit counter.
if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0. • Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e.
ATtiny261A/461A/861A • Bit 1 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
12. Timer/Counter1 12.1 Features • • • • • • • • • 12.
ATtiny261A/461A/861A For actual placement of the I/O pins, refer to “Pinout ATtiny261A/461A/861A” on page 2. The device-specific I/O register and bit locations are listed in the “Register Description” on page 111. 12.2.1 Speed The maximum speed of the Timer/Counter1 is 64 MHz. However, if a supply voltage below 2.7 volts is used, it is recommended to use the Low Speed Mode (LSM), because the Timer/Counter1 is not running fast enough on low voltage levels.
back right after writing the register. The read back values are delayed for the Timer/Counter1 (TCNT1) register, Timer/Counter1 High Byte Register (TC1H) and flags (OCF1A, OCF1B, OCF1D and TOV1), because of the input and output synchronization. The system clock frequency must be lower than half of the PCK frequency, because the synchronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of the PCK when the system clock is high.
ATtiny261A/461A/861A counter value and so on. The definitions in Table 12-1 are used extensively throughout the document. Table 12-1. 12.3 Definitions Constant Description BOTTOM The counter reaches BOTTOM when it becomes 0x00 MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255) TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register.
12.3.1.1 Prescaler Reset Setting the PSR1 bit in TCCR1B register resets the prescaler. It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. 12.3.1.2 Prescaler Initialization for Asynchronous Mode To change Timer/Counter1 to the asynchronous mode follow the procedure below: 1. Enable PLL. 2. Wait 100 µs for PLL to stabilize. 3. Poll the PLOCK bit until it is set. 4. Set the PCKE bit in the PLLCSR register which enables the asynchronous mode. 12.
ATtiny261A/461A/861A 12.4.1 Counter Initialization for Asynchronous Mode To set Timer/Counter1 to asynchronous mode follow the procedure below: 1. Enable PLL. 2. Wait 100 µs for PLL to stabilize. 3. Poll the PLOCK bit until it is set. 4. Set the PCKE bit in the PLLCSR register which enables the asynchronous mode. 12.5 Output Compare Unit The comparator continuously compares TCNT1 with the Output Compare Registers (OCR1A, OCR1B, OCR1C and OCR1D).
metrical PWM pulses, thereby making the output glitch-free. See Figure 12-6 for an example. During the time between the write and the update operation, a read from OCR1A, OCR1B, OCR1C or OCR1D will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A, OCR1B, OCR1C or OCR1D. Figure 12-6.
ATtiny261A/461A/861A 12.6 Dead Time Generator The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary output pairs OC1x and OC1x when the PWM mode is enabled and the COM1x[1:0] bits are set to “01”. See Figure 12-7 below. Figure 12-7.
zero. The outputs OC1x and OC1x are inverted, if the PWM Inversion Mode bit PWM1X is set. This will also cause both outputs to be high during the dead time. The length of the counting period is user adjustable by selecting the dead time prescaler setting by using the DTPS1[1:0] control bits, and selecting then the dead time value in I/O register DT1.
ATtiny261A/461A/861A Figure 12-10.
The design of the Output Compare Pin Configuration logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x[1:0] bit settings are reserved for certain modes of operation. For Output Compare Pin Configurations refer to Table 12-2 on page 99, Table 12-3 on page 101, Table 12-4 on page 103, Table 12-5 on page 104, Table 12-6 on page 104, and Table 12-7 on page 105. 12.7.1 12.
ATtiny261A/461A/861A The counter value (TCNT1) that is shown as a histogram in Figure 12-11 is incremented until the counter value matches the TOP value. The counter is then cleared at the following clock cycle The diagram includes the Waveform Output (OCW1x) in toggle Compare Mode. The small horizontal line marks on the TCNT1 slopes represent Compare Matches between OCR1x and TCNT1. The Timer/Counter Overflow Flag (TOV1) is set in the same clock cycle as the TCNT1 becomes zero.
DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. The timing diagram for the fast PWM mode is shown in Figure 12-12. The counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation.
ATtiny261A/461A/861A in a constantly high or low output (depending on the polarity of the output set by the COM1x[1:0] bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting the Waveform Output (OCW1x) to toggle its logical level on each Compare Match (COM1x[1:0] = 1). The waveform generated will have a maximum frequency of fOC1 = fclkT1/4 when OCR1C is set to three.
Figure 12-13. Phase and Frequency Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCWnx (COMnx = 2) OCWnx (COMnx = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In the Phase and Frequency Correct PWM mode, the compare unit allows generation of PWM waveforms on the OC1x pins.
ATtiny261A/461A/861A actual value from the port register will be visible on the port pin. The configurations of the Output Compare Pins are described in Table 12-4. Table 12-4. 12.8.4 Output Compare pin configurations in Phase and Frequency Correct PWM Mode COM1x1 COM1x0 OC1x Pin OC1x Pin 0 0 Disconnected Disconnected 0 1 OC1x OC1x 1 0 Disconnected OC1x 1 1 Disconnected OC1x PWM6 Mode The PWM6 Mode (PWM1A = 1, WGM1[1:0] = 1X) provide PWM waveform generation option e.g.
Figure 12-14. PWM6 Mode, Single-slope Operation, Timing Diagram TCNT1 OCW1A OC1OE0 OC1A Pin OC1OE1 OC1A Pin OC1OE2 OC1B Pin OC1OE3 OC1B Pin OC1OE4 OC1D Pin OC1OE5 OC1D Pin The general I/O port function is overridden by the Output Compare value (OC1x / OC1x) from the Dead Time Generator if either of the COM1x[1:0] bits are set. The Output Compare pins can also be overriden by the Output Compare Override Enable bits OC1OE5:OC1OE0.
ATtiny261A/461A/861A Table 12-7. 12.9 Configuration of Output Compare Pins OC1D and OC1D in PWM6 Mode COM1D1 COM1D0 OC1D Pin (PB4) OC1D Pin (PB5) 0 0 Disconnected Disconnected 0 1 OC1A • OC1OE4 OC1A • OC1OE5 1 0 OC1A • OC1OE4 OC1A • OC1OE5 1 1 OC1A • OC1OE4 OC1A • OC1OE5 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures.
Figure 12-17. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclkT1/8) clkPCK clkTn (clkPCK /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 12-18 shows the setting of TOV1 in Phase and Frequency Correct PWM Mode. Figure 12-18. Timer/Counter Timing Diagram, with Prescaler (fclkT1/8) clkPCK clkTn (clkPCK /8) TCNTn BOTTOM + 1 BOTTOM + 1 BOTTOM BOTTOM + 1 TOVn 12.
ATtiny261A/461A/861A pins. The Fault Protection Enable (FPEN1) is automatically cleared at the same system clock as the COM1nx bits are cleared. If the Fault Protection Interrupt Enable bit (FPIE1) is set, a Fault Protection interrupt is generated and the FPEN1 bit is cleared. Alternatively the FPEN1 bit can be polled by software to figure out when the Timer/Counter has entered to Fault Protection mode. 12.10.
12.11.2 Code Examples The following code examples show how to access the 10-bit timer registers assuming that no interrupts updates the TC1H register. The same principle can be used directly for accessing the OCR1A/B/C/D registers. Assembly Code Example ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TC1H,r17 out TCNT1,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1 in r17,TC1H ... C Code Example unsigned int i; ...
ATtiny261A/461A/861A The following code examples show how to do an atomic read of the TCNT1 register contents. Reading any of the OCR1A/B/C/D registers can be done by using the same principle.
The following code examples show how to do an atomic write of the TCNT1 register contents. Writing any of the OCR1A/B/C/D registers can be done by using the same principle.
ATtiny261A/461A/861A 12.12 Register Description 12.12.1 TCCR1A – Timer/Counter1 Control Register A Bit 7 6 5 4 3 2 1 0 0x30 (0x50) COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B PWM1A PWM1B Read/Write R/W R/W R/W R/W W W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR1A • Bits 7:6 – COM1A[1:0]: Comparator A Output Mode, Bits 1 and 0 These bits control the behaviour of the Waveform Output (OCW1A) and the connection of the Output Compare pin (OC1A).
Table 12-10 shows the COM1A[1:0] bit functionality when the PWM1A, WGM10 and WGM11 bits are set to Phase and Frequency Correct PWM Mode. Table 12-10. Compare Output Mode, Phase and Frequency Correct PWM Mode COM1A[1:0] OCW1A Behaviour OC1A Pin OC1A Pin 00 Normal port operation. Disconnected Disconnected 01 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Connected 10 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting.
ATtiny261A/461A/861A • Bits 5:4 – COM1B[1:0]: Comparator B Output Mode, Bits 1 and 0 These bits control the behaviour of the Waveform Output (OCW1B) and the connection of the Output Compare pin (OC1B). If one or both of the COM1B[1:0] bits are set, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. The complementary OC1B output is connected only in PWM modes when the COM1B[1:0] bits are set to “01”.
COM1B1S and COM1B0S in TCCR1C will show here. See “TCCR1C – Timer/Counter1 Control Register C” on page 116. • Bit 3 – FOC1A: Force Output Compare Match 1A The FOC1A bit is only active when the PWM1A bit specify a non-PWM mode. Writing a logical one to this bit forces a change in the Waveform Output (OCW1A) and the Output Compare pin (OC1A) according to the values already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written in the same cycle as FOC1A, the new settings will be used.
ATtiny261A/461A/861A The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can be generated. The Dead Time prescaler is controlled by two bits DTPS11 and DTPS10 from the Dead Time Prescaler register. These bits define the division factor of the Dead Time prescaler. The division factors are given in Table 12-16. Table 12-16.
12.12.3 TCCR1C – Timer/Counter1 Control Register C Bit 7 6 5 4 3 2 1 0 0x27 (0x47) COM1A1S COM1A0S COM1B1S COM1B0S COM1D1 COM1D0 FOC1D PWM1D Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR1C • Bits 7:6 – COM1A1S, COM1A0S: Comparator A Output Mode, Shadow Bits 1 and 0 These are shadow bits of COM1A1 and COM1A0 in TCCR1A. Writing to bits COM1A1S and COM1A0S will also change bits COM1A1 and COM1A0 in TCCR1A.
ATtiny261A/461A/861A Table 12-20 shows the COM1D[1:0] bit functionality when the PWM1D and WGM1[1:0] bits are set to Phase and Frequency Correct PWM Mode. Table 12-20. Compare Output Mode, Phase and Frequency Correct PWM Mode COM1D[1:0] OCW1D Behaviour OC1D Pin OC1D Pin 00 Normal port operation. Disconnected Disconnected 01 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Connected 10 Cleared on Compare Match when up-counting.
• Bit 3 – FPAC1: Fault Protection Analog Comparator Enable When written logic one, this bit enables the Fault Protection function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the Fault Protection front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Fault Protection interrupt.
ATtiny261A/461A/861A the Output Compare Override Enable Bit is cleared. Table 12-22 shows the Output Compare Override Enable Bits and their corresponding Output Compare pins. Table 12-22. Output Compare Override Enable Bits vs. Output Compare Pins 12.12.
12.12.7 TCNT1 – Timer/Counter1 Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCNT1 This 8-bit register contains the value of Timer/Counter1. The Timer/Counter1 is realized as a 10-bit up/down counter with read and write access.
ATtiny261A/461A/861A 12.12.10 OCR1B – Timer/Counter1 Output Compare Register B Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 OCR1B The output compare register B is an 8-bit read/write register. The Timer/Counter Output Compare Register B contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1.
Note that, if 10-bit accuracy is used special procedures must be followed when accessing the internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are described in section “Accessing 10-Bit Registers” on page 107. 12.12.
ATtiny261A/461A/861A the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 A compare match interrupt is executed. • Bit 5 – OCF1B: Output Compare Flag 1B The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1B - Output Compare Register 1A.
13. USI – Universal Serial Interface 13.1 Features • • • • • • 13.2 Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wakeup from Idle Mode In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode Two-wire Start Condition Detector with Interrupt Capability Overview The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication.
ATtiny261A/461A/861A The 4-bit counter can be both read and written via the data bus, and it can generate an overflow interrupt. The data register and the counter are clocked simultaneously by the same clock source, allowing the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges.
Figure 13-3. CYCLE Three-wire Mode, Timing Diagram ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The Three-wire mode timing is shown in Figure 13-3. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
ATtiny261A/461A/861A sbrs r16, USIOIF rjmp SPITransfer_loop lds r16,USIDR ret The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRA. The value stored in register r16 prior to the function is called is transferred to the slave device, and when the transfer is completed the data received from the slave is stored back into the register r16.
13.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<
ATtiny261A/461A/861A Figure 13-4. Two-wire Mode Operation, Simplified Diagram VCC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL HOLD SCL Two-wire Clock Control Unit SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL PORTxn MASTER The data direction is not given by the physical layer. A protocol, like the one used by the TWIbus, must be implemented to control the data flow. Figure 13-5.
3. The master set the first bit to be transferred and releases the SCL line (C). The slave samples the data and shifts it into the USI Data Register at the positive edge of the SCL clock. 4. After eight bits containing slave address and data direction (read or write) have been transferred, the slave counter overflows and the SCL line is forced low (D). If the slave is not the one the master has addressed, it releases the SCL line and waits for a new start condition. 5.
ATtiny261A/461A/861A 13.4.1 Half-Duplex Asynchronous Data Transfer Using the USI Data Register in three-wire mode it is possible to implement a more compact and higher performance UART than by software, only. 13.4.2 4-Bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the counter is clocked externally, both clock edges will increment the counter value. 13.4.
13.5.2 USIBR – USI Buffer Register Bit 7 6 5 4 3 2 1 0 0x10 (0x30) MSB LSB Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 USIBR The content of the Serial Register is loaded to the USI Buffer Register when the trasfer is completed, and instead of accessing the USI Data Register (the Serial Register) the USI Data Buffer can be accessed when the CPU reads the received data.
ATtiny261A/461A/861A The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe bits. The clock source depends of the setting of the USICS[1:0] bits. For external clock operation a special feature is added that allows the clock to be generated by writing to the USITC strobe bit.
Table 13-1. USIWM1 1 1 Note: Relationship between USIWM[1:0] and USI Operation (Continued) USIWM0 Description 0 Two-wire mode. Uses SDA (DI) and SCL (USCK) pins (1). The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and use open-collector output drives. The output drivers are enabled by setting the corresponding bit for SDA and SCL in the DDRA register.
ATtiny261A/461A/861A Table 13-2.
14. AC – Analog Comparator The analog comparator compares the input values on the selectable positive pin (AIN0, AIN1 or AIN2) and selectable negative pin (AIN0, AIN1 or AIN2). When the voltage on the positive pin is higher than the voltage on the negative pin, the Analog Comparator Output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the analog comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle.
ATtiny261A/461A/861A Table 14-1.
14.2 14.2.1 Register Description ACSRA – Analog Comparator Control and Status Register A Bit 7 6 5 4 3 2 1 0 0x08 (0x28) ACD ACBG ACO ACI ACIE ACME ACIS1 ACIS0 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 N/A 0 0 0 0 0 ACSRA • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the analog comparator is switched off.
ATtiny261A/461A/861A • Bits 1:0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 14-2. Table 14-2. ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge.
applied to the AREF pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 14.2.
ATtiny261A/461A/861A 15. ADC – Analog to Digital Converter 15.1 Features • • • • • • • • • • • • • • • • • • 15.2 10-bit Resolution 1.0 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 13 µs Conversion Time 15 kSPS at Maximum Resolution 11 Multiplexed Single Ended Input Channels 16 Differential input pairs 15 Differential input pairs with selectable gain Temperature Sensor Input Channel Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 1.1V / 2.
Figure 15-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ 15 ADC[9:0] ADPS1 ADPS0 ADPS2 ADATE ADIF ADEN ADSC ADLAR MUX1 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL. & STATUS REGISTER A (ADCSRA) MUX0 MUX3 MUX2 MUX4 REFS1 REFS0 ADC MULTIPLEXER SELECT (ADMUX) MUX5 REFS2 GSEL ADC CTRL. & STATUS REGISTER B (ADCSRB) ADIE ADIF 8-BIT DATA BUS PRESCALER MUX DECODER CHANNEL SELECTION AREF INTERNAL 2.56/1.
ATtiny261A/461A/861A reference may be decoupled by an external capacitor at the AREF pin to improve noise immunity. The analog input channel and differential gain are selected by writing to the MUX[5:0] bits in ADMUX. Any of the 11 ADC input pins ADC[10:0] can be selected as single ended inputs to the ADC. The positive and negative inputs to the differential gain amplifier are described in Table 15-5.
conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. Figure 15-2.
ATtiny261A/461A/861A The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. See Figure 15-3.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. See Figure 15-6. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. Figure 15-6.
ATtiny261A/461A/861A For a summary of conversion times, see Table 15-1. Table 15-1. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Total Conversion Time (Cycles) First conversion 13.5 25 Normal conversions 1.5 13 2 13.5 Condition Auto Triggered conversions 15.6 Changing Channel or Reference Selection The MUX[5:0] and REFS[2:0] bits in the ADCSRB and ADMUX registers are single buffered through a temporary register to which the CPU has random access.
selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. 15.6.2 15.7 ADC Voltage Reference The conversion range of the ADC is defined by the voltage reference (VREF). Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either VCC, or internal 1.1V / 2.56V voltage reference, or external AREF pin.
ATtiny261A/461A/861A Figure 15-8. Analog Input Circuitry IIH ADCn 1..100 kΩ CS/H= 14 pF IIL VCC/2 The capacitor in Figure 15-8 depicts the total capacitance, including the sample/hold capacitor and any stray or parasitic capacitance inside the device. The value given is worst case. The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less. If such a source is used, the sampling time will be negligible.
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 15-9. Offset Error Output Code Ideal ADC Actual ADC Offset Error VREF Input Voltage • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 15-10.
ATtiny261A/461A/861A • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 15-11. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.
• Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB. 15.
ATtiny261A/461A/861A ( V POS – V NEG ) ⋅ 512 ADC = ----------------------------------------------------- ⋅ GAIN V REF where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, and VREF the selected voltage reference. The result is presented in two’s complement form, from 0x200 (-512d) through 0x000 (+0d) to 0x1FF (+511d). The GAIN is either 1x, 8x, 20x or 32x.
15.13 Register Description 15.13.1 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 0x06 (0x26) ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
ATtiny261A/461A/861A Table 15-3. 15.13.2 15.13.2.1 ADPS2 ADPS1 ADPS0 Division Factor 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 ADCL and ADCH – The ADC Data Register ADLAR = 0 Bit 15 14 13 12 11 10 9 8 0x05 (0x25) – – – – – – ADC9 ADC8 ADCH 0x04 (0x24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write Initial Value 15.13.2.
• Bits 7:6 – REFS[1:0]: Voltage Reference Selection Bits These bits together with the REFS2 bit from the ADC Control and Status Register B (ADCSRB) select the voltage reference for the ADC, as shown in Table 15-4. Table 15-4. Voltage Reference Selections for ADC REFS2 REFS1 REFS0 Voltage Reference Selection X 0 0 VCC used as voltage reference, disconnected from AREF X 0 1 External voltage reference at AREF pin, internal voltage reference turned off 0 1 0 Internal 1.
ATtiny261A/461A/861A gain stage enables offset measurements. Selecting the single-ended channel ADC11 enables the temperature sensor. Refer to Table 15-5 for details. Table 15-5.
Table 15-5.
ATtiny261A/461A/861A If these bits are changed during a conversion, the change will not go into effect until this conversion is complete (ADIF in ADCSRA is set). 15.13.
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. Table 15-6. 15.13.
ATtiny261A/461A/861A 16. debugWIRE On-chip Debug System 16.1 Features • • • • • • • • • • 16.
When designing a system where debugWIRE will be used, the following must be observed: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. • Connecting the RESET pin directly to VCC will not work. • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 16.4 Software Break Points debugWIRE supports Program memory Break Points by the AVR Break instruction.
ATtiny261A/461A/861A 17. Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The SPM instruction is disabled by default but it can be enabled by programming the SELFPRGEN fuse (to “0”). The Program memory is updated in a page by page fashion.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 17.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. Note: 17.4 The CPU is halted during the Page Write operation.
ATtiny261A/461A/861A 17.5 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 17.
To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 Refer to Table 18-4 on page 169 for detailed description and mapping of the Fuse High Byte. To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and repeat the previous procedure.
ATtiny261A/461A/861A 17.9 17.9.1 Register Description SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory operations. Bit 7 6 5 4 3 2 1 0 0x37 (0x57) – – – CTPB RFLB PGWRT PGERS SPMEN Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPMCSR • Bits 7:5 – Res: Reserved Bits These bits are reserved and always read as zero.
18. Memory Programming This section describes the different methods for programming ATtiny261A/461A/861A memories. 18.1 Program And Data Memory Lock Bits The device provides two lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in Table 18-2. The lock bits can only be erased to “1” with the Chip Erase command. The device has no separate boot loader section.
ATtiny261A/461A/861A 18.2 Fuse Bytes The device has three fuse bytes. Table 18-3, Table 18-4 and Table 18-5 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 18-3.
Table 18-5. Fuse Low Byte Fuse Low Byte Description Default Value 7 Divide clock by 8 0 (programmed) CKOUT (2) 6 Clock Output Enable 1 (unprogrammed) SUT1 5 Select start-up time 1 (unprogrammed) (3) SUT0 4 Select start-up time 0 (programmed) (3) CKSEL3 3 Select Clock source 0 (programmed) (4) CKSEL2 2 Select Clock source 0 (programmed) (4) CKSEL1 1 Select Clock source 1 (unprogrammed) (4) CKSEL0 0 Select Clock source 0 (programmed) (4) CKDIV8 Notes: (1) Bit No 1.
ATtiny261A/461A/861A 18.5 Page Size Table 18-7. Device Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB ATtiny261A 1K words (2K bytes) 16 words PC[3:0] 64 PC[9:4] 9 ATtiny461A 2K words (4K bytes) 32 words PC[4:0] 64 PC[10:5] 10 ATtiny861A 4K words (8K bytes) 32 words PC[4:0] 128 PC[11:5] 11 Table 18-8. 18.6 No. of Words in a Page and No. of Pages in the Flash No. of Words in a Page and No. of Pages in the EEPROM Device EEPROM Size Page Size PCWORD No.
After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. Table 18-9. Note: Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PB0 I Serial Data in MISO PB1 O Serial Data out SCK PB2 I Serial Clock In Table 18-9, above, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface.
ATtiny261A/461A/861A before issuing the next page. (See Table 18-10.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written.
Table 18-11.
ATtiny261A/461A/861A Figure 18-2. Serial Programming Instruction example Serial Programming Instruction Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Byte 3 Adr MSB A Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 4 Byte 2 Adr LSB Bit 15 B Adr MSB Bit 15 B 0 Byte 3 Byte 4 Adrr LSB B 0 Page Buffer Page Offset Page 0 Page 1 Page 2 Page Number Page N-1 Program Memory/ EEPROM Memory 18.
Figure 18-3. Parallel Programming. +5V WR PB0 XA0 PB1 XA1/BS2 PB2 PAGEL/BS1 PB3 VCC +5V AVCC PA7 - PA0 DATA XTAL1/PB4 OE PB5 RDY/BSY PB6 +12 V RESET GND Table 18-12. Pin Name Mapping 176 Signal Name in Programming Mode Pin Name I/O WR PB0 I Write Pulse (Active low). XA0 PB1 I XTAL Action Bit 0 XA1/BS2 PB2 I XTAL Action Bit 1. Byte Select 2 (“0” selects low byte, “1” selects 2’nd high byte). PAGEL/BS1 PB3 I Byte Select 1 (“0” selects low byte, “1” selects high byte).
ATtiny261A/461A/861A Table 18-13. Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL/BS1 Prog_enable[3] 0 XA1/BS2 Prog_enable[2] 0 XA0 Prog_enable[1] 0 WR Prog_enable[0] 0 The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 18-14. Table 18-14. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1).
18.7.2 Entering Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3. Set Prog_enable pins listed in Table 18-13 on page 177 to “0000” and wait at least 100 ns. 4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied to RESET, will cause the device to fail entering programming mode. 5.
ATtiny261A/461A/861A 1. Load Command “Write Flash”: a. Set XA1, XA0 to “10”. This enables command loading. b. Set BS1 to “0”. c. Set DATA to “0001 0000”. This is the command for Write Flash. d. Give XTAL1 a positive pulse. This loads the command. 2. Load Address Low byte: a. Set XA1, XA0 to “00”. This enables address loading. b. Keep BS1 at “0”. This selects low address. c. Set DATA = Address low byte (0x00 - 0xFF). d. Give XTAL1 a positive pulse. This loads the address low byte. 3.
Figure 18-4. Addressing the Flash Which is Organized in Pages PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: PCPAGE and PCWORD are listed in Table 18-7 on page 171. In the figure below, “XX” means don’t care. The numbers in the figure refer to the programming description above. WR Figure 18-5.
ATtiny261A/461A/861A programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” on page 178 for details on Command, Address and Data loading): 1. A: Load Command “0001 0001”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. C: Load Data (0x00 - 0xFF). 5. E: Latch data (give PAGEL a positive pulse). 6. K: Repeat 3 through 5 until the entire buffer is filled. 7. L: Program EEPROM page a.
18.7.8 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” on page 178 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. 18.7.
ATtiny261A/461A/861A Figure 18-7. Programming the FUSES Waveforms Write Fuse Low byte DATA A C 0x40 DATA XX Write Fuse high byte A C 0x40 DATA XX Write Extended Fuse byte A C 0x40 DATA XX XA1/BS2 XA0 PAGEL/BS1 XTAL1 WR RDY/BSY RESET +12V OE 18.7.12 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 178 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte.
Figure 18-8. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read 0 Fuse Low Byte 0 Extended Fuse Byte 1 DATA BS2 0 Lock Bits 1 Fuse High Byte 1 BS1 BS2 18.7.14 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 178 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to “0”, and BS to “0”.
ATtiny261A/461A/861A 19. Electrical Characteristics 19.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied.
Table 19-1. DC Characteristics. TA = -40°C to +85°C, VCC = 1.8V to 5.5V (unless otherwise noted). Symbol Parameter Condition IIH Input Leakage Current I/O Pin VCC = 5.5V, pin high (absolute value) RRST Reset Pull-up Resistor RPU I/O Pin Pull-up Resistor Power Supply Current (7) ICC Power-down mode (8) Notes: Typ(1) Max Units < 0.05 1 µA 30 60 kΩ 20 50 kΩ Min Active 1MHz, VCC = 2V 0.2 0.5 mA Active 4MHz, VCC = 3V 1.2 2 mA Active 8MHz, VCC = 5V 3.
ATtiny261A/461A/861A 19.3 Speed The maximum operating frequency of the device is dependent on supply voltage, VCC . The relationship between supply voltage and maximum operating frequency is piecewise linear, as shown in Figure 19-1. Figure 19-1. Maximum Operating Frequency vs. Supply Voltage 20 MHz 10 MHz 4 MHz 1.8V 19.4 19.4.1 4.5V 5.
19.4.2 External Clock Drive Figure 19-2. External Clock Drive Waveforms V IH1 V IL1 Table 19-3. External Clock Drive Characteristics VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Min. Max. Min. Max. Min. Max. Units 0 4 0 10 0 20 MHz Symbol Parameter 1/tCLCL Clock Frequency tCLCL Clock Period 250 100 50 ns tCHCX High Time 100 40 20 ns tCLCX Low Time 100 40 20 ns tCLCH Rise Time 2.0 1.6 0.5 µs tCHCL Fall Time 2.0 1.6 0.
ATtiny261A/461A/861A 19.5.1 Enhanced Power-On Reset Table 19-5. Symbol Characteristics of Enhanced Power-On Reset. TA = -40 to +85°C Parameter Min(1) Typ(1) Max(1) Units 1.1 1.4 1.6 V 1.3 1.6 V (2) VPOR Release threshold of power-on reset VPOA Activation threshold of power-on reset (3) 0.6 SRON Power-On Slope Rate 0.01 Note: V/ms 1. Values are guidelines, only. 2. Threshold where device is released from reset when voltage is rising. 3.
19.6 ADC Characteristics Table 19-7. Symbol ADC Characteristics, Single Ended Channels. T = -40°C to +85°C Parameter Condition Min Typ Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Units 10 Bits VREF = 4V, VCC = 4V, ADC clock = 200 kHz 2 LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz 3 LSB VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 1.5 LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 2.
ATtiny261A/461A/861A Table 19-8. Symbol ADC Characteristics, Differential Channels (Unipolar Mode).
Table 19-9. Symbol ADC Characteristics, Differential Channels (Bipolar Mode).
ATtiny261A/461A/861A 19.7 Analog Comparator Characteristics Table 19-10. Analog Comparator Characteristics, TA = -40°C to +85°C Symbol Parameter Condition VAIO Input Offset Voltage VCC = 5V, VIN = VCC / 2 ILAC Input Leakage Current VCC = 5V, VIN = VCC / 2 Analog Propagation Delay (from saturation to slight overdrive) VCC = 2.7V 750 VCC = 4.0V 500 Analog Propagation Delay (large step change) VCC = 2.7V 100 VCC = 4.0V 75 Digital Propagation Delay VCC = 1.8V - 5.5 1 tAPD tDPD 19.
Table 19-11. Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V (Unless Otherwise Noted) Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL tCLCL Typ 0 Oscillator Period 1/tCLCL Max Units 4 MHz 250 Oscillator Frequency (VCC = 4.5V - 5.5V) 0 Oscillator Period VCC = 4.5V - 5.
ATtiny261A/461A/861A Figure 19-6. Parallel Programming Timing, Loading Sequence with Timing Requirements LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE) LOAD DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) t XLXH XTAL1 PAGEL/BS1 DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1/BS2 Note: The timing requirements shown in Figure 19-5 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 19-7.
Table 19-12.
ATtiny261A/461A/861A 20. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing.
Table 20-2. Additional Current Consumption (percentage) in Active and Idle mode. PRR bit Additional Current consumption compared to Active with external clock (see Figure 20-1 on page 199 and Figure 20-2 on page 199) Additional Current consumption compared to Idle with external clock (see Figure 20-6 on page 201 and Figure 20-7 on page 202) PRTIM1 20...25 % 100 % PRTIM0 2...3 % 10...15 % PRUSI 2...12 % 10...50% PRADC 15...100 % 50...
ATtiny261A/461A/861A 20.2 20.2.1 ATtiny261A Current Consumption in Active Mode Figure 20-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 1 5.5 V 0.8 5.0 V 4.5 V 0.4 3.3 V ICC (mA) 0.6 2.7 V 0.2 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 20-2. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY PRR = 0xFF 10 5.5 V 8 5.0 V 4.5 V ICC (mA) 6 4 3.3 V 2 2.7 V 1.
Figure 20-3. Active Supply Current vs. VCC (Internal Calibrated Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL OSCILLATOR, 8 MHz 5 85 °C 25 °C -40 °C 4 ICC (mA) 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-4. Active Supply Current vs. VCC (Internal Calibrated Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL OSCILLATOR, 1 MHz 1.2 85 °C 25 °C -40 °C 1 ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny261A/461A/861A Figure 20-5. Active Supply Current vs. VCC (Internal Calibrated Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL OSCILLATOR, 128 kHz 0.12 -40 °C 25 °C 85 °C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 20.2.2 Current Consumption in Idle Mode Figure 20-6. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0.14 5.5 V 0.12 5.0 V 0.1 ICC (mA) 4.5 V 0.08 4.0 V 0.06 3.3 V 2.
Figure 20-7. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 3 2.5 5.5 V 5.0 V 2 ICC (mA) 4.5 V 1.5 4.0 V 1 0.5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 20-8. Idle Supply Current vs. VCC (Internal Calibrated Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 8 MHz 1.4 85 °C 25 °C -40 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny261A/461A/861A Figure 20-9. Idle Supply Current vs. VCC (Internal Calibrated Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 1 MHz 0.35 85 °C 25 °C -40 °C 0.3 ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-10. Idle Supply Current vs. VCC (Internal Calibrated Oscillator, 128 kHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 128 kHz 0.025 -40 °C 25 °C 85 °C 0.02 ICC (mA) 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.
20.2.3 Current Consumption in Power-Down Mode Figure 20-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE WATCHDOG TIMER DISABLED 0.7 85 °C 0.6 ICC (uA) 0.5 0.4 0.3 0.2 25 °C 0.1 -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE WATCHDOG TIMER ENABLED 10 8 -40 °C 25 °C 85 °C ICC (uA) 6 4 2 0 1.5 2 2.
ATtiny261A/461A/861A 20.2.4 Current Consumption in Reset Figure 20-13. Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz, Excluding Current Through the Reset Pull-up) RESET CURRENT vs. FREQUENCY EXCLUDING CURRENT THROUGH RESET PULLUP 0.12 5.5 V 0.1 5.0 V ICC (mA) 0.08 4.5 V 4.0 V 0.06 3.3 V 2.7 V 0.04 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 20-14. Reset Supply Current vs.
20.2.5 Current Consumption of Peripheral Units Figure 20-15. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 80 70 60 ICC (uA) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 4 4.5 5 5.5 VCC (V) Figure 20-16. ADC Current vs. VCC (AREF = AVCC) ADC CURRENT vs. VCC f = 1.0 MHz 450 400 350 ICC (uA) 300 250 200 150 100 50 0 1.5 2 2.5 3 3.
ATtiny261A/461A/861A Figure 20-17. Timer/Counter1 Current vs. VCC TIMER/COUNTER1 CURRENT vs. VCC 8000 7000 64MHz 6000 ICC (uA) 5000 4000 32MHz 3000 2000 1000 1MHz 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-18. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 40 35 30 ICC (uA) 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 20-19. Programming Current vs. VCC PROGRAMMING CURRENT vs. VCC 8000 7000 6000 ICC (uA) 5000 4000 3000 2000 1000 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 20.2.6 Pull-up Resistors Figure 20-20. Pull-Up Resistor Current vs. Input Voltage (I/O Pin, VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 1.
ATtiny261A/461A/861A Figure 20-21. Pull-Up Resistor Current vs. Input Voltage (I/O Pin, VCC = 3V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 90 80 70 IOP (uA) 60 50 40 30 25 ˚C 20 85 ˚C 10 -40 ˚C 0 0 0,5 1 1,5 2 2,5 3 VOP (V) Figure 20-22. Pull-Up Resistor Current vs. Input Voltage (I/O Pin, VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs.
Figure 20-23. Pull-Up Resistor Current vs. Input Voltage (Reset Pin, VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 1.8V 40 35 30 IRESET (uA) 25 20 15 10 5 85 °C 25 °C -40 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VRESET (V) Figure 20-24. Pull-Up Resistor Current vs. Input Voltage (Reset Pin, VCC = 3V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 3V 60 50 IRESET (uA) 40 30 20 10 85 °C 25 °C -40 °C 0 0 0.5 1 1.5 2 2.
ATtiny261A/461A/861A Figure 20-25. Pull-Up Resistor Current vs. Input Voltage (Reset Pin, VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 5V 120 100 IRESET (uA) 80 60 40 20 85 °C 25 °C -40 °C 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V) 20.2.7 Output Driver Strength Figure 20-26. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 1.8V 0.4 0.35 85 °C 0.3 25 °C VOL (V) 0.25 -40 °C 0.2 0.15 0.1 0.
Figure 20-27. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 0.5 0.4 85 °C 25 °C VOL (V) 0.3 -40 °C 0.2 0.1 0 0 2 4 6 8 10 IOL (mA) Figure 20-28. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 0.7 0.6 VOL (V) 85 °C 0.5 25 °C 0.4 -40 °C 0.3 0.2 0.
ATtiny261A/461A/861A Figure 20-29. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 1.8V 1.8 1.7 VOH (V) 1.6 1.5 -40 °C 25 °C 1.4 85 °C 1.3 0 1 2 3 4 5 IOH (mA) Figure 20-30. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V 3 2.9 VOH (V) 2.8 2.7 -40 °C 25 °C 2.6 85 °C 2.
Figure 20-31. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5 VOH (V) 4.8 4.6 -40 °C 25 °C 4.4 85 °C 4.2 0 5 10 15 20 IOH (mA) Figure 20-32. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, VCC = 5V) OUTPUT VOLTAGE vs. SINK CURRENT RESET PIN AS I/O 0.8 85 °C VOL (V) 0.6 0.4 25 °C 0.2 -40 °C 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.
ATtiny261A/461A/861A Figure 20-33. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, T = 25°C) OUTPUT VOLTAGE vs. SINK CURRENT RESET PIN AS I/O 0.8 1.8 V VOL (V) 0.6 0.4 0.2 3.0 V 5.0 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 IOL (mA) Figure 20-34. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, VCC = 5V) OUTPUT VOLTAGE vs. SOURCE CURRENT RESET PIN AS I/O, VCC = 5V 5 4 85 °C 25 °C -40 °C VOH (V) 3 2 1 0 0 0.2 0.4 0.6 0.
Figure 20-35. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, T = 25°C) OUTPUT VOLTAGE vs. SOURCE CURRENT RESET PIN AS I/O 5 4 3 VOH (V) 5.0 V 2 3.0 V 1 1.8 V 0 0 0.2 0.4 0.6 0.8 1 IOH (mA) 20.2.8 Input Thresholds and Hysteresis Figure 20-36. VIH: Input Threshold Voltage vs. VCC (I/O Pin, Read as ‘1’) I/O PIN INPUT THRESHOLD vs. SUPPLY VOLTAGE VIH, I/O PIN READ AS '1' 3.5 3 85 °C 25 °C -40 °C Threshold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny261A/461A/861A Figure 20-37. VIL: Input Threshold Voltage vs. VCC (I/O Pin, Read as ‘0’) I/O PIN INPUT THRESHOLD vs. SUPPLY VOLTAGE VIL, I/O PIN READ AS '0' 3 85 °C 25 °C -40 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-38. VIH-VIL: Input Hysteresis vs. VCC (I/O Pin) I/O PIN INPUT HYSTERESIS vs. SUPPLY VOLTAGE 0.6 -40 °C Input Hysteresis (V) 0.5 0.4 25 °C 85 °C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 20-39. VIH: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘1’) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, PIN READ AS '1' 2.5 Threshold (V) 2 1.5 -40 °C 25 °C 85 °C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-40. VIL: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘0’) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, PIN READ AS '0' 2.5 -40 °C 25 °C 85 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny261A/461A/861A Figure 20-41. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin) RESET PIN INPUT HYSTERESIS vs. VCC 1 0.9 0.8 Input Hysteresis (V) 0.7 -40 °C 0.6 0.5 25 °C 0.4 85 °C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 20.2.9 BOD, Bandgap and Reset Figure 20-42. BOD Threshold vs. Temperature (BOD Level set to 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL = 4.3V 4.38 4.36 VCC RISING Threshold (V) 4.34 4.32 4.3 4.28 VCC FALLING 4.26 4.
Figure 20-43. BOD Threshold vs. Temperature (BOD Level set to 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL = 2.7V 2.78 2.76 VCC RISING Threshold (V) 2.74 2.72 2.7 VCC FALLING 2.68 2.66 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 20-44. BOD Threshold vs. Temperature (BOD Level set to 1.8V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL = 1.8V 1.85 1.84 Threshold (V) 1.83 VCC RISING 1.82 1.81 1.8 VCC FALLING 1.79 1.
ATtiny261A/461A/861A Figure 20-45. Bandgap Voltage vs. Supply Voltage. BANDGAP VOLTAGE vs. VCC 1.11 Bandgap Voltage (V) 1.1 85 °C 25 °C 1.09 1.08 -40 °C 1.07 1.5 2.5 3.5 4.5 5.5 VCC (V) Figure 20-46. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs. VCC 1800 1600 1400 Pulsewidth (ns) 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
20.2.10 Internal Oscillators Figure 20-47. Frequency of Watchdog Oscillator vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE 130000 Frequency (Hz) 125000 -40 °C 120000 25 °C 85 °C 115000 110000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-48. Frequency of Watchdog Oscillator vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 130000 Frequency (kHz) 125000 120000 1.8 V 3.0 V 5.
ATtiny261A/461A/861A Figure 20-49. Frequency of Calibrated 8.0 MHz Oscillator vs. VCC CALIBRATED 8MHz OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE 8.4 85 °C 25 °C 8.2 Frequency (MHz) -40 °C 8 7.8 7.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-50. Frequency of Calibrated 8.0 MHz Oscillator vs. Temperature CALIBRATED 8MHz OSCILLATOR FREQUENCY vs. TEMPERATURE 8.2 Frequency (MHz) 8.1 5.0 V 8 3.0 V 7.9 1.8 V 7.
Figure 20-51. Frequency of Calibrated 8.0 MHz Oscillator vs. OSCCAL Value CALIBRATED 8MHz OSCILLATOR FREQUENCY vs.
ATtiny261A/461A/861A 20.3 20.3.1 ATtiny461A Current Consumption in Active Mode Figure 20-52. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 1 5.5 V 0.8 5.0 V 4.5 V ICC (mA) 0.6 4.0 V 0.4 3.3 V 2.7 V 0.2 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 20-53. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY PRR = 0xFF 10 5.5 V 5.0 V 8 4.5 V ICC (mA) 6 4.0 V 4 3.3 V 2.
Figure 20-54. Active Supply Current vs. VCC (Internal Calibrated Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL OSCILLATOR, 8 MHz 5 85 °C 25 °C -40 °C 4 ICC (mA) 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-55. Active Supply Current vs. VCC (Internal Calibrated Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL OSCILLATOR, 1 MHz 1.2 85 °C 25 °C -40 °C 1 ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny261A/461A/861A Figure 20-56. Active Supply Current vs. VCC (Internal Calibrated Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL OSCILLATOR, 128 kHz 0.12 -40 °C 25 °C 85 °C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 20.3.2 Current Consumption in Idle Mode Figure 20-57. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0.14 5.5 V 0.12 5.0 V 4.5 V 0.1 ICC (mA) 4.0 V 0.08 3.3 V 0.
Figure 20-58. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 3 5.5 V 2.5 5.0 V 4.5 V ICC (mA) 2 1.5 4.0 V 1 3.3 V 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 20-59. Idle Supply Current vs. VCC (Internal Calibrated Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 8 MHz 1.4 85 °C 25 °C -40 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny261A/461A/861A Figure 20-60. Idle Supply Current vs. VCC (Internal Calibrated Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 1 MHz 0.35 85 °C 25 °C -40 °C 0.3 ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-61. Idle Supply Current vs. VCC (Internal Calibrated Oscillator, 128 kHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 128 kHz 0.025 -40 °C 85 °C 25 °C 0.02 ICC (mA) 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.
20.3.3 Current Consumption in Power-Down Mode Figure 20-62. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE WATCHDOG TIMER DISABLED 1.2 1 85 °C ICC (uA) 0.8 0.6 -40 °C 0.4 25 °C 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-63. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE WATCHDOG TIMER ENABLED 10 -40 °C 85 °C 8 25 °C ICC (uA) 6 4 2 0 1.5 2 2.5 3 3.
ATtiny261A/461A/861A 20.3.4 Current Consumption in Reset Figure 20-64. Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz, Excluding Current Through the Reset Pull-up) RESET CURRENT vs. FREQUENCY EXCLUDING CURRENT THROUGH RESET PULLUP 0.14 0.12 5.5 V 5.0 V 0.1 ICC (mA) 4.5 V 0.08 4.0 V 0.06 3.3 V 2.7 V 0.04 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 20-65. Reset Supply Current vs.
20.3.5 Current Consumption of Peripheral Units Figure 20-66. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 70 60 ICC (uA) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-67. ADC Current vs. VCC (AREF = AVCC) ADC CURRENT vs. VCC f = 1.0 MHz 400 350 300 ICC (uA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny261A/461A/861A Figure 20-68. Timer/Counter1 Current vs. VCC TIMER/COUNTER1 CURRENT vs. VCC 7000 64MHz 6000 ICC (uA) 5000 4000 32MHz 3000 2000 1000 1MHz 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-69. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 40 35 30 ICC (uA) 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 20-70. Programming Current vs. VCC PROGRAMMING CURRENT vs. VCC 8000 7000 6000 ICC (uA) 5000 4000 3000 2000 1000 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 20.3.6 Pull-up Resistors Figure 20-71. Pull-Up Resistor Current vs. Input Voltage (I/O Pin, VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 1.
ATtiny261A/461A/861A Figure 20-72. Pull-Up Resistor Current vs. Input Voltage (I/O Pin, VCC = 3V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 90 80 70 IOP (uA) 60 50 40 30 25 ˚C 20 85 ˚C 10 -40 ˚C 0 0 0,5 1 1,5 2 2,5 3 VOP (V) Figure 20-73. Pull-Up Resistor Current vs. Input Voltage (I/O Pin, VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs.
Figure 20-74. Pull-Up Resistor Current vs. Input Voltage (Reset Pin, VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 1.8V 40 35 30 IRESET (uA) 25 20 15 10 5 -40 °C 25 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VRESET (V) Figure 20-75. Pull-Up Resistor Current vs. Input Voltage (Reset Pin, VCC = 3V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 3V 60 50 IRESET (uA) 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.
ATtiny261A/461A/861A Figure 20-76. Pull-Up Resistor Current vs. Input Voltage (Reset Pin, VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 5V 120 100 IRESET (uA) 80 60 40 20 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V) 20.3.7 Output Driver Strength Figure 20-77. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 1.8V 0.4 85 °C 0.35 0.3 25 °C VOL (V) 0.25 -40 °C 0.2 0.15 0.1 0.
Figure 20-78. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 0.45 0.4 85 °C 0.35 25 °C VOL (V) 0.3 -40 °C 0.25 0.2 0.15 0.1 0.05 0 0 2 4 6 8 10 IOL (mA) Figure 20-79. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 0.7 0.6 VOL (V) 85 °C 0.5 25 °C 0.4 -40 °C 0.3 0.2 0.
ATtiny261A/461A/861A Figure 20-80. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 1.8V 1.8 VOL (V) 1.6 -40 °C 25 °C 1.4 85 °C 1.2 0 1 2 3 4 5 IOL (mA) Figure 20-81. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V 3 VOL (V) 2.8 -40 °C 25 °C 2.6 85 °C 2.
Figure 20-82. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5 VOL (V) 4.8 4.6 -40 °C 25 °C 4.4 85 °C 4.2 0 5 10 15 20 IOL (mA) Figure 20-83. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, VCC = 5V) OUTPUT VOLTAGE vs. SINK CURRENT RESET PIN AS I/O, VCC = 5V 0.6 85 °C 0.5 25 °C 0.4 VOL (V) -40 °C 0.3 0.2 0.1 0 0 0.5 1 1.5 2 2.
ATtiny261A/461A/861A Figure 20-84. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, T = 25°C) OUTPUT VOLTAGE vs. SINK CURRENT RESET PIN AS I/O 0.5 1.8 V 0.4 VOL (V) 0.3 0.2 3.0 V 5.0 V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 IOL (mA) Figure 20-85. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, VCC = 5V) OUTPUT VOLTAGE vs. SOURCE CURRENT RESET PIN AS I/O, VCC = 5V 5 4 -40 °C 25 °C 85 °C VOH (V) 3 2 1 0 0 0.2 0.4 0.6 0.
Figure 20-86. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, T = 25°C) OUTPUT VOLTAGE vs. SOURCE CURRENT RESET PIN AS I/O 5 4 3 VOH (V) 5.0 V 2 3.0 V 1 1.8 V 0 0 0.2 0.4 0.6 0.8 1 IOH (mA) 20.3.8 Input Thresholds and Hysteresis Figure 20-87. VIH: Input Threshold Voltage vs. VCC (I/O Pin, Read as ‘1’) I/O PIN INPUT THRESHOLD vs. SUPPLY VOLTAGE VIH, I/O PIN READ AS '1' 3.5 85 °C 25 °C -40 °C 3 Threshold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny261A/461A/861A Figure 20-88. VIL: Input Threshold Voltage vs. VCC (I/O Pin, Read as ‘0’) I/O PIN INPUT THRESHOLD vs. SUPPLY VOLTAGE VIL, I/O PIN READ AS '0' 3 -40 °C 25 °C 85 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-89. VIH-VIL: Input Hysteresis vs. VCC (I/O Pin) I/O PIN INPUT HYSTERESIS vs. SUPPLY VOLTAGE 0.6 0.5 85 °C 25 °C Input Hysteresis (V) -40 °C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 20-90. VIH: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘1’) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, PIN READ AS '1' 2.5 Threshold (V) 2 1.5 -40 °C 25 °C 85 °C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-91. VIL: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘0’) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, PIN READ AS '0' 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny261A/461A/861A Figure 20-92. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin) RESET PIN INPUT HYSTERESIS vs. VCC 1 0.9 0.8 Input Hysteresis (V) 0.7 0.6 -40 °C 0.5 25 °C 0.4 0.3 85 °C 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 20.3.9 BOD, Bandgap and Reset Figure 20-93. BOD Threshold vs. Temperature (BOD Level set to 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL = 4.3V 4.4 4.38 VCC RISING Threshold (V) 4.36 4.34 4.32 VCC FALLING 4.3 4.28 4.26 4.
Figure 20-94. BOD Threshold vs. Temperature (BOD Level set to 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL = 2.7V 2.8 2.78 VCC RISING Threshold (V) 2.76 2.74 2.72 VCC FALLING 2.7 2.68 2.66 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 20-95. BOD Threshold vs. Temperature (BOD Level set to 1.8V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL = 1.8V 1.86 1.85 Threshold (V) 1.84 VCC RISING 1.83 1.82 1.81 VCC FALLING 1.8 1.79 1.
ATtiny261A/461A/861A Figure 20-96. Bandgap Voltage vs. Supply Voltage. BANDGAP VOLTAGE vs. VCC 1.12 Bandgap Voltage (V) 1.11 85 °C 25 °C 1.1 1.09 1.08 -40 °C 1.07 1.5 2.5 3.5 4.5 5.5 VCC (V) Figure 20-97. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs. VCC 1800 1600 1400 Pulsewidth (ns) 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
20.3.10 Internal Oscillators Figure 20-98. Frequency of Watchdog Oscillator vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE 120000 115000 Frequency (Hz) -40 °C 25 °C 110000 85 °C 105000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-99. Frequency of Watchdog Oscillator vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE Frequency (kHz) 120000 115000 1.8 V 110000 3.0 V 5.
ATtiny261A/461A/861A Figure 20-100. Frequency of Calibrated 8.0 MHz Oscillator vs. VCC CALIBRATED 8MHz OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE 8.4 25 °C Frequency (MHz) 8.2 85 °C -40 °C 8 7.8 7.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-101. Frequency of Calibrated 8.0 MHz Oscillator vs. Temperature CALIBRATED 8MHz OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE 8.4 Frequency (MHz) 8.2 5.0 V 8 3.0 V 1.8 V 7.8 7.
Figure 20-102. Frequency of Calibrated 8.0 MHz Oscillator vs. OSCCAL Value CALIBRATED 8MHz OSCILLATOR FREQUENCY vs.
ATtiny261A/461A/861A 20.4 20.4.1 ATtiny861A Current Consumption in Active Mode Figure 20-103. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 1 5.5 V 0.8 5.0 V 4.5 V ICC (mA) 0.6 4.0 V 0.4 3.3 V 2.7 V 0.2 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 20-104. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY PRR = 0xFF 10 5.5 V 5.0 V 8 4.5 V ICC (mA) 6 4.0 V 4 3.3 V 2.
Figure 20-105. Active Supply Current vs. VCC (Internal Calibrated Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL OSCILLATOR, 8 MHz 5 -40 °C 25 °C 85 °C 4 ICC (mA) 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-106. Active Supply Current vs. VCC (Internal Calibrated Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL OSCILLATOR, 1 MHz 1.2 -40 °C 25 °C 85 °C 1 ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny261A/461A/861A Figure 20-107. Active Supply Current vs. VCC (Internal Calibrated Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL OSCILLATOR, 128 kHz 0.12 -40 °C 25 °C 85 °C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 20.4.2 Current Consumption in Idle Mode Figure 20-108. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0.14 0.12 5.5 V 5.0 V 0.1 ICC (mA) 4.5 V 0.08 4.0 V 0.06 3.
Figure 20-109. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 3 2.5 5.5 V 5.0 V 2 ICC (mA) 4.5 V 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 20-110. Idle Supply Current vs. VCC (Internal Calibrated Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 8 MHz 1.4 -40 °C 85 °C 25 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny261A/461A/861A Figure 20-111. Idle Supply Current vs. VCC (Internal Calibrated Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 1 MHz 0.35 -40 °C 85 °C 25 °C 0.3 ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-112. Idle Supply Current vs. VCC (Internal Calibrated Oscillator, 128 kHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 128 kHz 0.025 -40 °C 85 °C 25 °C 0.02 ICC (mA) 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.
20.4.3 Current Consumption in Power-Down Mode Figure 20-113. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE WATCHDOG TIMER DISABLED 0.8 85 °C 0.7 0.6 ICC (uA) 0.5 0.4 0.3 25 °C 0.2 -40 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-114. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE WATCHDOG TIMER ENABLED 10 8 -40 °C 85 °C 25 °C ICC (uA) 6 4 2 0 1.5 2 2.
ATtiny261A/461A/861A 20.4.4 Current Consumption in Reset Figure 20-115. Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz, Excluding Current Through the Reset Pull-up) RESET CURRENT vs. FREQUENCY EXCLUDING CURRENT THROUGH RESET PULLUP 0.12 5.5 V 0.1 5.0 V ICC (mA) 0.08 4.5 V 4.0 V 0.06 3.3 V 0.04 2.7 V 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 20-116. Reset Supply Current vs.
20.4.5 Current Consumption of Peripheral Units Figure 20-117. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 80 70 60 ICC (uA) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-118. ADC Current vs. VCC (AREF = AVCC) ADC CURRENT vs. VCC f = 1.0 MHz 400 350 300 ICC (uA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny261A/461A/861A Figure 20-119. Timer/Counter1 Current vs. VCC TIMER/COUNTER1 CURRENT vs. VCC 6000 64MHz 5000 ICC (uA) 4000 32MHz 3000 2000 1000 1MHz 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-120. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 40 35 30 ICC (uA) 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 20-121. Programming Current vs. VCC PROGRAMMING CURRENT vs. VCC 16000 14000 12000 ICC (uA) 10000 8000 6000 4000 2000 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 20.4.6 Pull-up Resistors Figure 20-122. Pull-Up Resistor Current vs. Input Voltage (I/O Pin, VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 1.
ATtiny261A/461A/861A Figure 20-123. Pull-Up Resistor Current vs. Input Voltage (I/O Pin, VCC = 3V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 90 80 70 IOP (uA) 60 50 40 30 25 ˚C 20 85 ˚C 10 -40 ˚C 0 0 0,5 1 1,5 2 2,5 3 VOP (V) Figure 20-124. Pull-Up Resistor Current vs. Input Voltage (I/O Pin, VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs.
Figure 20-125. Pull-Up Resistor Current vs. Input Voltage (Reset Pin, VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 1.8V 40 35 30 IRESET (uA) 25 20 15 10 5 -40 °C 25 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VRESET (V) Figure 20-126. Pull-Up Resistor Current vs. Input Voltage (Reset Pin, VCC = 3V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 3V 60 50 IRESET (uA) 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.
ATtiny261A/461A/861A Figure 20-127. Pull-Up Resistor Current vs. Input Voltage (Reset Pin, VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 5V 120 100 IRESET (uA) 80 60 40 20 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V) 20.4.7 Output Driver Strength Figure 20-128. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 1.8V 0.4 0.35 85 °C 0.3 25 °C VOL (V) 0.25 -40 °C 0.2 0.15 0.1 0.
Figure 20-129. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 0.4 85 °C 0.35 25 °C 0.3 -40 °C VOL (V) 0.25 0.2 0.15 0.1 0.05 0 0 2 4 6 8 10 IOL (mA) Figure 20-130. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 0.6 85 °C 0.5 25 °C VOL (V) 0.4 -40 °C 0.3 0.2 0.
ATtiny261A/461A/861A Figure 20-131. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 1.8V 1.8 VOL (V) 1.6 -40 °C 25 °C 1.4 85 °C 1.2 0 1 2 3 4 5 IOL (mA) Figure 20-132. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V 3 VOL (V) 2.8 -40 °C 25 °C 2.6 85 °C 2.
Figure 20-133. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5 VOL (V) 4.8 4.6 -40 °C 25 °C 4.4 85 °C 4.2 0 5 10 15 20 IOL (mA) Figure 20-134. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, VCC = 5V) OUTPUT VOLTAGE vs. SINK CURRENT RESET PIN AS I/O, VCC = 5V 0.6 85 °C 0.5 25 °C VOL (V) 0.4 -40 °C 0.3 0.2 0.1 0 0 0.5 1 1.5 2 2.
ATtiny261A/461A/861A Figure 20-135. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, T = 25°C) OUTPUT VOLTAGE vs. SINK CURRENT RESET PIN AS I/O 0.5 1.8 V 0.4 VOL (V) 0.3 0.2 3.0 V 5.0 V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 IOL (mA) Figure 20-136. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, VCC = 5V) OUTPUT VOLTAGE vs. SOURCE CURRENT RESET PIN AS I/O, VCC = 5V 5 4 3 VOH (V) 25 °C 85 °C 2 -40 °C 1 0 0 0.2 0.4 0.6 0.
Figure 20-137. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, T = 25°C) OUTPUT VOLTAGE vs. SOURCE CURRENT RESET PIN AS I/O 5 4 3 VOH (V) 5.0 V 2 3.0 V 1 1.8 V 0 0 0.2 0.4 0.6 0.8 1 IOH (mA) 20.4.8 Input Thresholds and Hysteresis Figure 20-138. VIH: Input Threshold Voltage vs. VCC (I/O Pin, Read as ‘1’) I/O PIN INPUT THRESHOLD vs. SUPPLY VOLTAGE VIH, I/O PIN READ AS '1' 3.5 85 °C 25 °C -40 °C 3 Threshold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny261A/461A/861A Figure 20-139. VIL: Input Threshold Voltage vs. VCC (I/O Pin, Read as ‘0’) I/O PIN INPUT THRESHOLD vs. SUPPLY VOLTAGE VIL, I/O PIN READ AS '0' 3 -40 °C 25 °C 85 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-140. VIH-VIL: Input Hysteresis vs. VCC (I/O Pin) I/O PIN INPUT HYSTERESIS vs. SUPPLY VOLTAGE 0.6 85 °C 25 °C -40 °C Input Hysteresis (V) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 20-141. VIH: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘1’) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, PIN READ AS '1' 2.5 Threshold (V) 2 1.5 1 -40 °C 25 °C 85 °C 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-142. VIL: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘0’) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, PIN READ AS '0' 2.5 -40 °C 25 °C 85 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny261A/461A/861A Figure 20-143. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin) RESET PIN INPUT HYSTERESIS vs. VCC 1 0.9 0.8 Input Hysteresis (V) 0.7 -40 °C 0.6 0.5 25 °C 0.4 85 °C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 20.4.9 BOD, Bandgap and Reset Figure 20-144. BOD Threshold vs. Temperature (BOD Level set to 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL = 4.3V VCC RISING 4.36 4.34 Threshold (V) 4.32 4.3 4.28 VCC FALLING 4.26 4.24 4.
Figure 20-145. BOD Threshold vs. Temperature (BOD Level set to 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL = 2.7V 2.78 2.76 VCC RISING Threshold (V) 2.74 2.72 2.7 VCC FALLING 2.68 2.66 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 20-146. BOD Threshold vs. Temperature (BOD Level set to 1.8V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL = 1.8V 1.84 1.83 VCC RISING Threshold (V) 1.82 1.81 1.8 VCC FALLING 1.79 1.
ATtiny261A/461A/861A Figure 20-147. Bandgap Voltage vs. Supply Voltage. BANDGAP VOLTAGE vs. VCC 1.11 85 °C Bandgap Voltage (V) 1.1 25 °C 1.09 -40 °C 1.08 1.07 1.5 2.5 3.5 4.5 5.5 VCC (V) Figure 20-148. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs. VCC 1800 1600 1400 Pulsewidth (ns) 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
20.4.10 Internal Oscillators Figure 20-149. Frequency of Watchdog Oscillator vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE 115000 -40 °C Frequency (Hz) 110000 25 °C 105000 85 °C 100000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-150. Frequency of Watchdog Oscillator vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE Frequency (kHz) 115000 110000 1.8 V 3.0 V 105000 5.
ATtiny261A/461A/861A Figure 20-151. Frequency of Calibrated 8.0 MHz Oscillator vs. VCC CALIBRATED 8MHz OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE 8.4 -40 °C 25 °C Frequency (MHz) 8.2 85 °C 8 7.8 7.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 20-152. Frequency of Calibrated 8.0 MHz Oscillator vs. Temperature CALIBRATED 8MHz OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE 8.4 Frequency (MHz) 8.2 8 5.0 V 3.0 V 7.8 1.8 V 7.
Figure 20-153. Frequency of Calibrated 8.0 MHz Oscillator vs. OSCCAL Value CALIBRATED 8MHz OSCILLATOR FREQUENCY vs.
ATtiny261A/461A/861A 21.
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them.
ATtiny261A/461A/861A 22.
Mnemonics Operands Description Operation Flags #Clocks ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..
ATtiny261A/461A/861A 23. Ordering Information 23.1 ATtiny261A Power Supply Ordering Code (1) 20 20 Speed (MHz) Notes: Package (2) Operational Range 1.8 – 5.5V ATtiny261A-MU ATtiny261A-MUR ATtiny261A-PU ATtiny261A-SU ATtiny261A-SUR ATtiny261A-XU ATtiny261A-XUR 32M1-A 32M1-A 20P3 20S2 20S2 20X 20X Industrial (-40°C to +85°C) (3) 1.8 – 5.5V ATtiny261A-MN ATtiny261A-MNR 32M1-A 32M1-A Industrial (-40°C to +105°C) (4) 1. Code indicators: – N or U: matte tin – R: tape & reel 2.
23.2 ATtiny461A Speed (MHz) 20 Notes: Power Supply Ordering Code (1) 1.8 – 5.5V ATtiny461A-MU ATtiny461A-MUR ATtiny461A-PU ATtiny461A-SU ATtiny461A-SUR ATtiny461A-XU ATtiny461A-XUR Package (2) Operational Range 32M1-A 32M1-A 20P3 20S2 20S2 20X 20X Industrial (-40°C to +85°C) (3) 1. Code indicators: – U: matte tin – R: tape & reel 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). 3.
ATtiny261A/461A/861A 23.3 ATtiny861A Speed (MHz) 20 Notes: Power Supply Ordering Code (1) 1.8 – 5.5V ATtiny861A-MU ATtiny861A-MUR ATtiny861A-PU ATtiny861A-SU ATtiny861A-SUR ATtiny861A-XU ATtiny861A-XUR Package (2) Operational Range 32M1-A 32M1-A 20P3 20S2 20S2 20X 20X Industrial (-40°C to +85°C) (3) 1. Code indicators: – U: matte tin – R: tape & reel 2.
24. Packaging Information 24.1 32M1-A D D1 1 2 3 0 Pin 1 ID E1 SIDE VIEW E TOP VIEW A3 A2 A1 A K 0.08 C P D2 1 2 3 P Pin #1 Notch (0.20 R) K e SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A3 E2 b COMMON DIMENSIONS (Unit of Measure = mm) L BOTTOM VIEW 0.20 REF b 0.18 0.23 D 4.90 5.00 5.10 D1 4.70 4.75 4.80 D2 2.95 3.10 3.25 E 4.90 5.00 5.10 0.30 E1 4.70 4.75 4.80 E2 2.95 3.10 3.25 e Note: JEDEC Standard MO-220, Fig.
ATtiny261A/461A/861A 24.2 20P3 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). SYMBOL MIN NOM MAX A – – 5.334 A1 0.381 – – D 25.493 – 25.984 E 7.620 – 8.255 E1 6.096 – 7.112 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.
24.
ATtiny261A/461A/861A 24.4 20X Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AC INDEX MARK PIN 1 4.50 (0.177) 6.50 (0.256) 4.30 (0.169) 6.25 (0.246) 6.60 (.260) 6.40 (.252) 0.65 (.0256) BSC 0.30 (0.012) 0.19 (0.007) 1.20 (0.047) MAX 0.15 (0.006) 0.05 (0.002) SEATING PLANE 0.20 (0.008) 0.09 (0.004) 0º ~ 8º 0.75 (0.030) 0.45 (0.018) 10/23/03 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 20X, (Formerly 20T), 20-lead, 4.
25. Errata 25.1 Errata ATtiny261A The revision letter in this section refers to the revision of the ATtiny261A device. 25.1.1 Rev D No known errata. 25.1.2 Rev C Not sampled. 25.2 Errata ATtiny461A The revision letter in this section refers to the revision of the ATtiny461A device. 25.2.1 Rev C No known errata. 25.3 Errata ATtiny861A The revision letter in this section refers to the revision of the ATtiny861A device. 25.3.1 Rev D No known errata. 25.3.2 Rev C Not sampled.
ATtiny261A/461A/861A 26. Datasheet Revision History 26.1 Rev. 8197C – 05/11 1. Added: – Section 3.3 “Capacitive Touch Sensing” on page 6 – Section 4. “CPU Core” on page 7 – Table 6-10, “Capacitance of Low-Frequency Crystal Oscillator,” on page 29 – Table 15-5 on page 157 – Section 19.7 “Analog Comparator Characteristics” on page 193 – Table 19-8 on page 191 – Table 19-9 on page 192 – Tape & reel part numbers in Section 23.
– “OSCCAL – Oscillator Calibration Register” on page 32 – “MCUCR – MCU Control Register” on page 38 – “MCUCR – MCU Control Register” on page 51 – “MCUCR – MCU Control Register” on page 68 – “Speed” on page 187 – “Enhanced Power-On Reset” on page 189 – “ATtiny261A” on page 199 – “Register Summary” on page 277 5. Updated tables: – “DC Characteristics. TA = -40°C to +85°C, VCC = 1.8V to 5.5V (unless otherwise noted).
ATtiny261A/461A/861A Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1 2 Overview ................................................................................................... 4 2.1 3 4 5 6 7 Pin Descriptions ................................................................................................
8 9 7.2 Software BOD Disable .....................................................................................36 7.3 Power Reduction Register ...............................................................................37 7.4 Minimizing Power Consumption ......................................................................37 7.5 Register Description ........................................................................................38 System Control and Reset ...........................
ATtiny261A/461A/861A 12.5 Output Compare Unit .......................................................................................93 12.6 Dead Time Generator ......................................................................................95 12.7 Compare Match Output Unit ............................................................................96 12.8 Modes of Operation .........................................................................................98 12.
16.4 Software Break Points ...................................................................................162 16.5 Limitations of debugWIRE .............................................................................162 16.6 Register Description ......................................................................................162 17 Self-Programming the Flash ............................................................... 163 17.1 Performing Page Erase by SPM ................................
ATtiny261A/461A/861A 20.4 ATtiny861A ....................................................................................................251 21 Register Summary ............................................................................... 277 22 Instruction Set Summary .................................................................... 279 23 Ordering Information ........................................................................... 281 23.1 ATtiny261A ............................................
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