Datasheet

50
2586D–AVR–02/06
ATtiny25/45/85
11.2.3 GIFR – General Interrupt Flag Register
• Bits 7, 4:0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
• Bit 5 – PCIF: Pin Change Interrupt Flag
When a logic change on any PCINT5:0 pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
11.2.4 PCMSK – Pin Change Mask Register
• Bits 7, 6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bits 5:0 – PCINT5:0: Pin Change Enable Mask 5:0
Each PCINT5:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
If PCINT5:0 is set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the corre-
sponding I/O pin. If PCINT5:0 is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
Bit 76543210
0x3A –INTF0PCIF–––––GIFR
Read/WriteRR/WR/WRRRRR
Initial Value00000000
Bit 76543210
0x15 – – PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value00111111