Datasheet

2586D–AVR–02/06

ATtiny25/45/85

8.4 Power Reduction Register

The Power Reduction Register, PRR, provides a method to stop the clock to individualperipher-

als to reduce power consumption. The current state of the peripheral is frozenand the I/O

registers can not be read or written. Resources used by the peripheral when stopping the clock

will remain occupied, hence the peripheral should in most cases be disabled before stopping the

clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the

same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. See “Power-Down Supply Current” on page TBD for examples. In all other

sleep modes, the clock is already stopped

8.4.1 PRR – Power Reduction Register

• Bits 7:4- Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bit 3- PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1

is enabled, operation will continue like before the shutdown.

• Bit 2- PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0

is enabled, operation will continue like before the shutdown.

• Bit 1 - PRUSI: Power Reduction USI

Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When

waking up the USI again, the USI should be re initialized to ensure proper operation.

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.

The analog comparator cannot use the ADC input MUX when the ADC is shut down.

8.5 Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR

controlled system. In general, sleep modes should be used as much as possible, and the sleep

mode should be selected so that as few as possible of the device’s functions are operating. All

functions not needed should be disabled. In particular, the following modules may need special

consideration when trying to achieve the lowest possible power consumption.

8.5.1 Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

abled before entering any sleep mode. When the ADC is turned off and on again, the next

Bit 76543 2 10

0x20 – - - - PRTIM1 PRTIM0 PRUSI PRADC PRR

Read/WriteRRRRR/WR/WR/WR/W

Initial Value 0 0 0 0 0 0 0 0