Datasheet

33
2586D–AVR–02/06
ATtiny25/45/85
8.1 Idle Mode
When the SM1:0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing Analog Comparator, ADC, USI, Timer/Counter, Watchdog, and
the interrupt system to continue operating. This sleep mode basically halts clk
CPU
and clk
FLASH
,
while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,
the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator
Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the
ADC is enabled, a conversion starts automatically when this mode is entered.
8.2 ADC Noise Reduction Mode
When the SM1:0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise
Reduction mode, stopping the CPU but allowing the ADC, USI, the external interrupts, and the
Watchdog to continue operating (if enabled). This sleep mode halts clk
I/O
, clk
CPU
, and clk
FLASH
,
while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change
interrupt can wake up the MCU from ADC Noise Reduction mode.
8.3 Power-down Mode
When the SM1:0 bits are written to 10, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the Oscillator is stopped, while the external interrupts, the USI start
condition detection and the Watchdog continue operating (if enabled). Only an External Reset, a
Watchdog Reset, a Brown-out Reset, USI start condition interupt, an external level interrupt on
INT0 or a pin change interrupt can wake up the MCU. This sleep mode halts all generated
clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to ”External Interrupts” on page 48
for details
..
Note: 1. For INT0, only level interrupt.
Table 8-2. Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Active Clock Domains Oscillators Wake-up Sources
Sleep Mode
clk
CPU
clk
FLASH
clk
IO
clk
ADC
clk
PCK
Main Clock Source Enabled INT0 and Pin Change SPM/EEPROM Ready USI Start Condition ADC Other I/O Watchdog Interrupt
Idle XXX X XXXXXX
ADC Noise
Reduction
XXX
(1)
XXX X
Power-down X
(1)
XX