Datasheet
29
2586D–AVR–02/06
ATtiny25/45/85
7.7.1 High Frequency PLL Clock - PLL
CLK
There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator
for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as
a system clock source, by programming the CKSEL fuses to ‘0001’, it is divided by four like
shown in Table 7-11. When this clock source is selected, start-up times are determined by the
SUT fuses as shown in Table 7-12. See also ”PCK Clocking System” on page 23.
7.8 128 kHz Internal Oscillator
The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-
quency is nominal at 3V and 25°C. This clock may be select as the system clock by
programming the CKSEL Fuses to “11”.
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 7-13.
7.9 Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. Note that the clock will not be output during reset and the normal operation
of I/O pin will be overridden when the fuse is programmed. Any clock source, including the inter-
nal RC Oscillator, can be selected when the clock is output on CLKO. If the System Clock
Prescaler is used, it is the divided system clock that is output.
Table 7-11. PLLCK Operating Modes
CKSEL3:0 Nominal Frequency
0001 16 MHz
Table 7-12. Start-up Times for the PLLCK
SUT1:0
Start-up Time from
Power Down
Additional Delay from Reset
(V
CC
= 5.0V)
Recommended
usage
00 14CK + 1K (1024) CK + 4 ms 14CK + 1K (1024) CK + 8ms BOD enabled
01 14CK + 16K (16384) CK + 4 ms 14CK + 16K (16384) CK + 8ms Fast rising power
10 14CK + 1K (1024) CK + 64 ms 14CK + 1K (1024) CK + 68 ms Slowly rising power
11 14CK + 16K (16384) CK + 64 ms 14CK + 1K (1024) CK + 68 ms Slowly rising power
Table 7-13. Start-up Times for the 128 kHz Internal Oscillator
SUT1:0
Start-up Time from
Power-down
Additional Delay from
Reset Recommended Usage
00 6 CK 14CK BOD enabled
01 6 CK 14CK + 4 ms Fast rising power
10 6 CK 14CK + 64 ms Slowly rising power
11 Reserved