Datasheet
148
2586D–AVR–02/06
ATtiny25/45/85
used. If a reset occurs while a write operation is in progress, the write operation will be
completed provided that the power supply voltage is sufficient.
2. Keep the AVR core in Power-down sleep mode during periods of low V
CC
. This will pre-
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
22.1.5 Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 22-1 shows the typical pro-
gramming time for Flash accesses from the CPU.
Table 22-1. SPM Programming Time
Symbol Min Programming Time Max Programming Time
Flash write (Page Erase, Page Write, and
write Lock bits by SPM)
3.7 ms 4.5 ms