Datasheet

129
2586D–AVR–02/06
ATtiny25/45/85
Figure 20-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 20-7. ADC Timing Diagram, Free Running Conversion
20.5 Changing Channel or Reference Selection
The MUX3:0 and REFS2:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and voltage refer-
ence selection only takes place at a safe point during the conversion. The channel and voltage
reference selection is continuously updated until a conversion is started. Once the conversion
starts, the channel and voltage reference selection is locked to ensure a sufficient sampling time
for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion
Table 20-1. ADC Conversion Time
Condition
Sample & Hold
(Cycles from Start of Conversion) Conversion Time (Cycles)
First conversion 13.5 25
Normal conversions 1.5 13
Auto Triggered conversions 2 13.5
1 2 3 4 5 6 7 8
9
10 11 12 13
Sign and MSB of Resul
t
LSB of Result
A
DC Clock
T
rigger
S
ource
A
DIF
A
DCH
A
DCL
C
ycle Number
12
One Conversion Next Conversio
n
Conversion
Complete
Prescaler
Reset
A
DATE
Prescaler
Reset
Sample &
Hold
MUX and REFS
Update
11 12 13
Sign and MSB of Result
LSB of Result
A
DC Clock
A
DSC
A
DIF
A
DCH
A
DCL
C
ycle Number
12
One Conversion Next Conversion
34
Conversion
Complete
Sample & Ho
ld
MUX and REFS
Update