Datasheet

107
2586D–AVR–02/06
ATtiny25/45/85
consists of two 4-bit fields, DT1xH and DT1xL that control the dead time periods of the PWM
output and its’ complementary output separately. Thus the rising edge of OC1x and OC1x
can
have different dead time periods. The dead time is adjusted as the number of prescaled dead
time generator clock cycles.
Figure 17-3. The Complementary Output Pair
17.0.1 DTPS1 – Timer/Counter1 Dead Time Prescaler Register 1
The dead time prescaler register, DTPS1 is a 2-bit read/write register.
The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the
Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can
be generated. The Dead Time prescaler is controlled by two bits DTPS11..10 from the Dead
Time Prescaler register. These bits define the division factor of the Dead Time prescaler. The
division factors are given in table 46..
17.0.2 DT1A – Timer/Counter1 Dead Time A
The dead time value register A is an 8-bit read/write register.
O
C1x
x
= A or B
t
non-overlap / rising edge
t
non-overlap / falling edge
O
C1x
P
WM1x
Bit 76543210
0x23
DTPS11 DTPS10 DTPS1
Read/Write RRRRRRR/WR/W
Initial value 0 0 0 0 0 0 0 0
Table 17-1. Division factors of the Dead Time prescaler
DTPS11 DTPS10 Prescaler divides the T/C1 clock by
0 0 1x (no division)
012x
104x
118x
Bit 76543210
0x25 DT1AH3 DT1AH2 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 DT1A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0