Datasheet

100
2586D–AVR–02/06
ATtiny25/45/85
The Stop condition provides a Timer Enable/Disable function.
16.2.2 GTCCR – General Timer/Counter1 Control Register
• Bit 2- FOC1A: Force Output Compare Match 1A
Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A)
according to the values already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written
in the same cycle as FOC1A, the new settings will be used. The Force Output Compare bit can
be used to change the output pin value regardless of the timer value. The automatic action pro-
grammed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no
interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit
is set.
• Bit 1- PSR1 : Prescaler Reset Timer/Counter1
When this bit is set (one), the Timer/Counter prescaler (TCNT1 is unaffected) will be reset. The
bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have
no effect. This bit will always read as zero.
16.2.3 TCNT1 – Timer/Counter1
This 8-bit register contains the value of Timer/Counter1.
Timer/Counter1 is realized as an up counter with read and write access. Due to synchronization
of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one CPU clock cycle
in synchronous mode and at most two CPU clock cycles for asynchronous mode.
1000CK/8
1001CK/16
1010CK/32
1011CK/64
1100CK/128
1101CK/256
1110CK/512
1 1 1 1 CK/1024
Table 16-2. Timer/Counter1 Prescale Select (Continued)
CS13 CS12 CS11 CS10 T/C1 Clock
Bit 7 6 5 4 3 2 1 0
0x2C
TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 GTCCR
Read/Write R/W R/W R/W R/W W W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 76543210
0x2F MSB LSB TCNT1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0