Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-volatile Program and Data Memories – 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny25/45/85) Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes In-System Programmable EEPROM (ATtiny25/45/85) Endurance: 100,000 Write/Erase Cycles –
1. Pin Configurations Figure 1-1.
ATtiny25/45/85 2. Overview The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1.
registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATtiny25/45/85 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation.
5. AVR CPU Core 5.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 5.2 Architectural Overview Figure 5-1.
ATtiny25/45/85 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
5.4.1 SREG – AVR Status Register The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 0x3F I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
ATtiny25/45/85 5.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
15 Y-register YH YL 7 0 R29 (0x1D) Z-register 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 5.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls.
ATtiny25/45/85 Figure 5-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 5-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 5-5.
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present.
ATtiny25/45/85 5.8.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles.
6. AVR Memories This section describes the different memories in the ATtiny25/45/85. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny25/45/85 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 6.1 In-System Re-programmable Flash Program Memory The ATtiny25/45/85 contains 2/4/8K byte On-chip In-System Reprogrammable Flash memory for program storage.
ATtiny25/45/85 When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of internal data SRAM in the ATtiny25/45/85 are all accessible through all these addressing modes. The Register File is described in ”General Purpose Register File” on page 9. Figure 6-2.
6.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 6-1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down.
ATtiny25/45/85 6.3.4 EECR – EEPROM Control Register Bit 7 6 5 4 3 2 1 0 0x1C – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0 EECR • Bit 7 – Res: Reserved Bit This bit is reserved for future use and will always read as 0 in ATtiny25/45/85. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit.
• Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation.
ATtiny25/45/85 Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set Programming mode ldi r16, (0<
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATtiny25/45/85 6.4 I/O Memory The I/O space definition of the ATtiny25/45/85 is shown in ”Register Summary” on page 194. All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
7. System Clock and Clock Options 7.1 Clock Systems and their Distribution Figure 7-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ”Power Management and Sleep Modes” on page 32. The clock systems are detailed below. Figure 7-1.
ATtiny25/45/85 7.1.5 Internal PLL for Fast Peripheral Clock Generation - clkPCK The internal PLL in ATtiny25/45/85 generates a clock frequency that is 8x multiplied from a source input. The source of the PLL input clock is the output of the internal RC oscillator having a frequency of 8.0 MHz. Thus the output of the PLL, the fast peripheral clock is 64 MHz. The fast peripheral clock, or a clock prescaled from that, can be selected as the clock source for Timer/Counter1. See the Figure 7-2 on page 23.
7.2 Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Device Clocking Options Select(1) Table 7-1. Device Clocking Option CKSEL3:0 External Clock 0000 PLL Clock 0001 Calibrated Internal RC Oscillator 8.0 MHz 0010 Calibrated Internal RC Oscillator 6.
ATtiny25/45/85 Figure 7-3. Crystal Oscillator Connections C2 C1 XTAL2 XTAL1 GND The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 7-3. Table 7-3. Crystal Oscillator Operating Modes CKSEL3:1 Frequency Range (MHz) Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) 100(1) 0.4 - 0.9 – 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.
Notes: 7.5 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up.
ATtiny25/45/85 ing a 4x multiplied frequency from the reference clock. The resulting frequency is 25.6 MHz and it is needed for supporting the same PWM frequencies as in ATtiny15. Table 7-6. Internal Calibrated RC Oscillator Operating Modes CKSEL3:0 Nominal Frequency (1) 8.0 MHz 0010 0011 Note: 6.4 MHz 1. The device is shipped with this option selected.
quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80. The CAL6:0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. Incrementing CAL6:0 by 1 will give a frequency increment of less than 2% in the frequency range 7.3 - 8.1 MHz.
ATtiny25/45/85 7.7.1 High Frequency PLL Clock - PLLCLK There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as a system clock source, by programming the CKSEL fuses to ‘0001’, it is divided by four like shown in Table 7-11. When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 7-12. See also ”PCK Clocking System” on page 23.
7.10 System Clock Prescaler The ATtiny25/45/85 system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 7-14. 7.10.
ATtiny25/45/85 device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 7-14. 7.10.
8. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.
ATtiny25/45/85 8.1 Idle Mode When the SM1:0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing Analog Comparator, ADC, USI, Timer/Counter, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow.
8.4 Power Reduction Register The Power Reduction Register, PRR, provides a method to stop the clock to individualperipherals to reduce power consumption. The current state of the peripheral is frozenand the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock.
ATtiny25/45/85 conversion will be an extended conversion. Refer to ”Analog to Digital Converter” on page 124 for details on ADC operation. 8.5.2 Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically disabled.
9. System Control and Reset 9.0.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 9-1 shows the reset logic.
ATtiny25/45/85 Reset Characteristics(1) Table 9-1. Symbol Parameter VPOT Min Typ Max Units Power-on Reset Threshold Voltage (rising) TA = -40 - 85°C 0.7 1.0 1.4 V Power-on Reset Threshold Voltage (falling)(2) TA = -40 - 85°C 0.6 0.9 1.3 V 0.2 VCC 0.9 VCC V 2.5 µs VRST RESET Pin Threshold Voltage VCC = 3V tRST Minimum pulse width on RESET Pin VCC = 3V Notes: 9.0.3 Condition 1. Values are guidelines only. Actual values are TBD. 2.
Figure 9-3. MCU Start-up, RESET Extended Externally VPOT VCC VRST RESET tTOUT TIME-OUT INTERNAL RESET 9.0.4 External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see Table 9-1) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
ATtiny25/45/85 Table 9-2. BODLEVEL Fuse Coding(1) BODLEVEL [2:0] Fuses Note: Min VBOT Typ VBOT 110 1.8 101 2.7 100 4.3 011 2.3 010 2.2 001 1.9 000 2.0 Max VBOT Units V 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test.
Figure 9-6. Watchdog Reset During Operation CC CK 9.0.7 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 7 6 5 4 3 2 1 0 0x34 – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 See Bit Description MCUSR • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
ATtiny25/45/85 9.1.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 9-4. To save power, the reference is not always turned on. The reference is on during the following situations: 1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse). 2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR). 3. When the ADC is enabled.
Watchdog Timer OSC/512K OSC/1024K OSC/256K OSC/64K OSC/128K OSC/8K OSC/4K OSC/2K WATCHDOG RESET OSC/32K WATCHDOG PRESCALER 128 kHz OSCILLATOR OSC/16K Figure 9-7. WDP0 WDP1 WDP2 WDP3 WDE MCU RESET 9.2.
ATtiny25/45/85 description of the WDE bit for a Watchdog disable procedure. This bit must also be set when changing the prescaler bits. See Section “9.3” on page 44. • Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed: 1.
Table 9-7. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V Reserved The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATtiny25/45/85 9.3.1 Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to one without any restriction. A timed sequence is needed when disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2.
10. Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny25/45/85. For a general explanation of the AVR interrupt handling, refer to ”Reset and Interrupt Handling” on page 11. 10.1 Interrupt Vectors in ATtiny25/45/85 Table 10-1. Reset and Interrupt Vectors Vector No.
ATtiny25/45/85 0x000C rjmp WDT ; 0x000D rjmp USI_START ; rjmp USI_OVF ; 0x000E 0x000F RESET: ldi 0x0010 ldi r17, high(RAMEND); Tiny45/85 also has SPH 0x0011 out SPL, r16 ; Set Stack Pointer to top of RAM 0x0012 out SPH, r17 ; Tiny45/85 als has SPH 0x0013 sei 0x0014 ... ... r16, low(RAMEND); Main program start ; Enable interrupts xxx ... ...
11. External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT5..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT5..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. Pin change interrupts PCI will trigger if any enabled PCINT5..0 pin toggles. The PCMSK Register control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT5..0 are detected asynchronously.
ATtiny25/45/85 11.2 11.2.1 External Interrupts Register Description MCUCR – MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control.
11.2.3 GIFR – General Interrupt Flag Register Bit 7 6 5 4 3 2 1 0x3A – INTF0 PCIF – – – – 0 – Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 GIFR • Bits 7, 4:0 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).
ATtiny25/45/85 12. I/O Ports 12.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 12.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 12-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 12-2.
ATtiny25/45/85 If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 12.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 12.2.
Figure 12-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
ATtiny25/45/85 Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
12.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATtiny25/45/85 12.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 12-5 shows how the port pin control signals from the simplified Figure 12-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 12-5.
Table 12-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 12-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 12-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
ATtiny25/45/85 12.3.1 MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 – PUD SE SM1 SM0 – ISC01 ISC00 Read/Write R R/W R/W R/W R/W R R R Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bits 7, 2– Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
ADC0: Analog to Digital Converter, Channel 0. PCINT5: Pin Change Interrupt source 5. • Port B, Bit 4- XTAL2/CLKO/ADC2/OC1B/PCINT4 XTAL2: Chip Clock Oscillator pin 2. Used as clock pin for all chip clock sources except internal calibrateble RC Oscillator and external clock. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC Oscillator or External clock as a Chip clock sources, PB4 serves as an ordinary I/O pin.
ATtiny25/45/85 enabled as a Slave, the data direction of this pin is controlled by DDB1. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB1 bit. AIN1: Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. OC0B: Output Compare Match output.
Table 12-4.
ATtiny25/45/85 12.4 12.4.1 12.4.2 12.4.
13. 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation. The main features are: • • • • • • • 13.
ATtiny25/45/85 The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). See Section “13.4” on page 66. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request. 13.1.
Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
ATtiny25/45/85 Figure 13-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes. Be aware that the COM0x1:0 bits are not double buffered together with the compare value.
ATtiny25/45/85 13.5.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 13-2 on page 75. For fast PWM mode, refer to Table 13-3 on page 75, and for phase correct PWM refer to Table 13-4 on page 76.
Figure 13-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATtiny25/45/85 PWM mode is shown in Figure 13-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 13-6.
feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 13.6.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5.
ATtiny25/45/85 one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 13-4 on page 76). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output.
Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 13-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 13-10.
ATtiny25/45/85 13.8 8-bit Timer/Counter Register Description 13.8.1 TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x2A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM01A:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior.
Table 13-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 13-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting.
ATtiny25/45/85 Table 13-4 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 13-7. COM0A1 COM0A0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. Note: Description 1.
13.8.2 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0x33 FOC0A FOC0B – – WGM02 CS02 CS01 0 CS00 Read/Write W W R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
ATtiny25/45/85 Table 13-9. Clock Select Bit Description (Continued) CS02 CS01 CS00 Description 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output.
13.8.6 TIMSK – Timer/Counter Interrupt Mask Register Bit 7 6 5 4 3 2 1 0x39 – OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 0 – Read/Write R R R R R/W R/W R/W R Initial Value 0 0 0 0 0 0 0 0 TIMSK • Bits 7:5, 0 – Res: Reserved Bits These bits are reserved bits and will always read as zero.
ATtiny25/45/85 • Bit 1 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting.
14. Timer/Counter Prescaler The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. 14.0.1 Prescaler Reset The prescaler is free running, i.e.
ATtiny25/45/85 and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 14-2. Prescaler for Timer/Counter0 clk I/O Clear PSR10 T0 Synchronization clkT0 Note: 14.0.3 1. The synchronization logic on the input pins (T0) is shown in Figure 14-1.
15. 8-bit Timer/Counter1 The Timer/Counter1 is a general purpose 8-bit Timer/Counter module that has a separate prescaling selection from the separate prescaler. Figure 15-1 shows the Timer/Counter1 prescaler that supports two clocking modes, a syncrhonous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base.
ATtiny25/45/85 this function. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Figure 15-2. Timer/Counter 1 Synchronization Register Block Diagram.
Figure 15-3. Timer/Counter1 Block Diagram T/C1 OVER- T/C1 COMPARE T/C1 COMPARE FLOW IRQ MATCH A IRQ MATCH B IRQ OC1A (PB1) OC1B (PB4) OC1A (PB0) DEAD TIME GENERATOR PSR1 FOC1B FOC1A COM1B0 PWM1B GLOBAL T/C CONTROL REGISTER (GTCCR) COM1B1 CS10 CS11 CS12 CS13 COM1A0 COM1A1 CTC1 TOV1 T/C CONTROL REGISTER 1 (TCCR1) PWM1A TOV1 TOV0 OCF1B OCF1A OCF1A TIMER INT. FLAG REGISTER (TIFR) OCF1B TOIE1 TOIE0 OCIE1B OCIE1A DEAD TIME GENERATOR TIMER INT.
ATtiny25/45/85 15.1.1 TCCR1 – Timer/Counter1 Control Register Bit 7 6 5 4 3 2 1 0 CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0x30 TCCR1 • Bit 7- CTC1 : Clear Timer/Counter on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.
Table 15-2. Timer/Counter1 Prescale Select (Continued) Asynchronous Clocking Mode Synchronous Clocking Mode 1 PCK/64 CK/64 0 0 PCK/128 CK/128 0 0 1 PCK/256 CK/256 1 0 1 0 PCK/512 CK/512 1 0 1 1 PCK/1024 CK/1024 1 1 0 0 PCK/2048 CK/2048 1 1 0 1 PCK/4096 CK/4096 1 1 1 0 PCK/8192 CK/8192 1 1 1 1 PCK/16384 CK/16384 CS13 CS12 CS11 CS10 0 1 1 1 0 1 The Stop condition provides a Timer Enable/Disable function. 15.1.
ATtiny25/45/85 in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1B1 and COM1B0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1B bit always reads as zero. FOC1B is not in use if PWM1B bit is set.
15.1.5 OCR1B – Timer/Counter1 Output Compare RegisterB Bit 7 6 5 4 3 2 1 0 0x2B MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 OCR1B The output compare register B is an 8-bit read/write register. The Timer/Counter Output Compare Register B contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts to the OCR1B value.
ATtiny25/45/85 • Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR. • Bit 0 - Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. 15.1.
15.1.9 PLLCSR – PLL Control and Status Register Bit 7 6 5 4 3 2 1 0 LSM - - - - PCKE PLLE PLOCK Read/Write R R R R R R/W R/W R Initial value 0 0 0 0 0 0 0/1 0 0x27 PLLCSR • Bit 7 - LSM: Low Speed Mode The high speed mode is enabled as default and the fast peripheral clock is 64 MHz, but the low speed mode can be set by writing the LSM bit to one. Then the fast peripheral clock is scaled down to 32 MHz. The low speed mode must be set, if the supply voltage is below 2.
ATtiny25/45/85 Figure 15-4. The PWM Output Pair PWM1x PWM1x t non-overlap =0 t non-overlap =0 x = A or B When the counter value match the contents of OCR1A or OCR1B, the OC1A and OC1B outputs are set or cleared according to the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register A - TCCR1, as shown in Table 15-4. Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output compare register OCR1C, and starting from $00 up again.
Figure 15-5. Effects of Unsynchronized OCR Latching Compare Value changes Counter Value Compare Value PWM Output OC1x Synchronized OC1x Latch Compare Value changes Counter Value Compare Value PWM Output OC1x Glitch Unsynchronized OC1x Latch During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A or OCR1B.
ATtiny25/45/85 Table 15-6. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode PWM Frequency Clock Selection CS13:CS10 OCR1C RESOLUTION 20 kHz PCK/16 0101 199 7.6 30 kHz PCK/16 0101 132 7.1 40 kHz PCK/8 0100 199 7.6 50 kHz PCK/8 0100 159 7.3 60 kHz PCK/8 0100 132 7.1 70 kHz PCK/4 0011 228 7.8 80 kHz PCK/4 0011 199 7.6 90 kHz PCK/4 0011 177 7.5 100 kHz PCK/4 0011 159 7.3 110 kHz PCK/4 0011 144 7.2 120 kHz PCK/4 0011 132 7.
16. 8-bit Timer/Counter1 in ATtiny15 Mode The ATtiny15 compatibility mode is selected by writing the code “0011” to the CKSEL fuses (if any other code is written, the Timer/Counter1 is working in normal mode). When selected the ATtiny15 compatibility mode provides an ATtiny15 backward compatible prescaler and Timer/Counter. Furthermore, the clocking system has same clock frequencies as in ATtiny15. 16.1 Timer/Counter1 Prescaler Figure 16-1 shows an ATtiny15 compatible prescaler.
ATtiny25/45/85 Figure 16-2. Timer/Counter 1 Synchronization Register Block Diagram.
Figure 16-3. Timer/Counter1 Block Diagram PSR1 GLOBAL T/C CONTROL REGISTER 2 (GTCCR) FOC1A CS10 CS12 CS11 CS13 COM1A1 COM1A0 T/C CONTROL REGISTER 1 (TCCR1) CTC1 PWM1A TOV1 TOV0 OCF1A TIMER INT. FLAG REGISTER (TIFR) OCF1A TIMER INT.
ATtiny25/45/85 16.2.1 TCCR1 – Timer/Counter1 Control Register Bit 7 6 5 4 3 2 1 0 CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0x30 TCCR1A • Bit 7- CTC1 : Clear Timer/Counter on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1A register.
Table 16-2. Timer/Counter1 Prescale Select (Continued) CS13 CS12 CS11 CS10 T/C1 Clock 1 0 0 0 CK/8 1 0 0 1 CK/16 1 0 1 0 CK/32 1 0 1 1 CK/64 1 1 0 0 CK/128 1 1 0 1 CK/256 1 1 1 0 CK/512 1 1 1 1 CK/1024 The Stop condition provides a Timer Enable/Disable function. 16.2.
ATtiny25/45/85 16.2.4 OCR1A – Timer/Counter1 Output Compare RegisterA Bit 7 6 5 4 3 2 1 0 0x2E MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 OCR1A The output compare register A is an 8-bit read/write register. The Timer/Counter Output Compare Register A contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts to the OCR1A value.
• Bit 0 - Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. 16.2.7 TIFR – Timer/Counter Interrupt Flag Register Bit 7 6 5 4 3 2 1 0x38 - OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 0 - Read/Write R R/W R/W R R R/W R/W R Initial value 0 0 0 0 0 0 0 0 TIFR • Bit 7 - Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
ATtiny25/45/85 16.2.9 Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register A OCR1A form an 8-bit, free-running and glitch-free PWM generator with output on the PB1(OC1A). When the counter value match the content of OCR1A, the OC1A and output is set or cleared according to the COM1A1/COM1A0 bits in the Timer/Counter1 Control Register A - TCCR1, as shown in Table 16-3.
When OCR1A contains $00 or the top value, as specified in OCR1C register, the output PB1(OC1A) is held low or high according to the settings of COM1A1/COM1A0. This is shown in Table 16-4. Table 16-4. PWM Outputs OCR1A = $00 or OCR1C COM1A1 COM1A0 OCR1A Output OC1A 0 1 $00 L 0 1 OCR1C H 1 0 $00 L 1 0 OCR1C H 1 1 $00 H 1 1 OCR1C L In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C value and the TCNT1 is reset to $00.
ATtiny25/45/85 Table 16-5. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode PWM Frequency Clock Selection CS13..CS10 OCR1C RESOLUTION 20 kHz PCK/16 0101 199 7.6 30 kHz PCK/16 0101 132 7.1 40 kHz PCK/8 0100 199 7.6 50 kHz PCK/8 0100 159 7.3 60 kHz PCK/8 0100 132 7.1 70 kHz PCK/4 0011 228 7.8 80 kHz PCK/4 0011 199 7.6 90 kHz PCK/4 0011 177 7.5 100 kHz PCK/4 0011 159 7.3 110 kHz PCK/4 0011 144 7.2 120 kHz PCK/4 0011 132 7.
17. Dead Time Generator The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be connected to Timer/Counter1 and it is used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary output pairs (OC1A-OC1A and OC1B-OC1B).
ATtiny25/45/85 consists of two 4-bit fields, DT1xH and DT1xL that control the dead time periods of the PWM output and its’ complementary output separately. Thus the rising edge of OC1x and OC1x can have different dead time periods. The dead time is adjusted as the number of prescaled dead time generator clock cycles. Figure 17-3. The Complementary Output Pair PWM1x OC1x OC1x x = A or B t non-overlap / rising edge 17.0.
The dead time delay of is adjusted by the dead time value register, DT1A. The register consists of two fields, DT1AH3..0 and DT1AL3..0, one for each complementary output. Therefore a different dead time delay can be adjusted for the rising edge of OC1A and the rising edge of OC1A. • Bits 7:4- DT1AH3:DT1AH0: Dead Time Value for OC1A Output The dead time value for the OC1A output. The dead time delay is set as a number of the prescaled timer/counter clocks.
ATtiny25/45/85 18. USI – Universal Serial Interface The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load. The main features of the USI are: • • • • • • 18.
an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the number of bits. The clock can be selected from three different sources: The USCK pin, Timer/Counter0 Compare Match or from software. The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus.
ATtiny25/45/85 Figure 18-3. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The Three-wire mode timing is shown in Figure 18-3. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
rjmp SPITransfer_loop lds r16,USIDR ret The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is called is transferred to the Slave device, and when the transfer is completed the data received from the Slave is stored back into the r16 Register. The second and third instructions clears the USI Counter Overflow Flag and the USI counter value.
ATtiny25/45/85 18.2.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<
Figure 18-4. Two-wire Mode Operation, Simplified Diagram VCC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL HOLD SCL Two-wire Clock Control Unit SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL PORTxn MASTER Figure 18-4 shows two USI units operating in Two-wire mode, one as Master and one as Slave. It is only the physical layer that is shown since the system operation is highly dependent of the communication scheme used.
ATtiny25/45/85 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the corresponding bit in the PORT Register to zero. Note that the Data Direction Register bit must be set to one for the output to be enabled. The slave device’s start detector logic (Figure 18-6.) detects the start condition and sets the USISIF Flag.
18.3 Alternative USI Usage When the USI unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible design. 18.3.1 Half-duplex Asynchronous Data Transfer By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact and higher performance UART than by software only. 18.3.2 4-bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt.
ATtiny25/45/85 18.4.2 USIBR – USI Buffer Register Bit 7 0x10 MSB 6 5 4 3 2 1 Read/Write Initial Value 0 R R R R R R R R 0 0 0 0 0 0 0 0 LSB USIBR The content of the Serial Register is loaded to the USI Buffer Register when the trasfer is completed, and instead of accessing the USI Data Register (the Serial Register) the USI Data Buffer can be accessed when the CPU reads the received data.
The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe bits. The clock source depends of the setting of the USICS1..0 bits. For external clock operation a special feature is added that allows the clock to be generated by writing to the USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an external clock source (USICS1 = 1).
ATtiny25/45/85 Table 18-1. Relations between USIWM1..0 and the USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode. However, the corresponding DDR bit still controls the data direction. When the port pin is set as input the pins pull-up is controlled by the PORT bit.
Table 18-2 shows the relationship between the USICS1..0 and USICLK setting and clock source used for the Shift Register and the 4-bit counter. Table 18-2. Relations between the USICS1..
ATtiny25/45/85 19. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle.
disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. • Bit 6 – ACBG: Analog Comparator Bandgap Select When this bit is set an internal 1.1V / 2.56V reference voltage replaces the positive input to the Analog Comparator. The selection of the internal voltage reference is done by writing the REFS2..0 bits in ADMUX register. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator.
ATtiny25/45/85 19-2. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog Comparator. Table 19-2. 19.1.1 Analog Comparator Multiplexed Input ACME ADEN MUX1..
20. Analog to Digital Converter 20.1 Features • • • • • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 65 - 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution Four Multiplexed Single Ended Input Channels Two differential input channels with selectable gain Temperature sensor input channel Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 1.1V / 2.
ATtiny25/45/85 Figure 20-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] AREF INTERNAL 1.1V/2.56V REFERENCE PRESCALER START CONVERSION LOGIC TEMPERATURE SENSOR SAMPLE & HOLD COMPARATOR 10-BIT DAC ADC4 ADC3 ADC2 ADC[9:0] ADPS1 ADPS0 ADPS2 ADIF ADSC ADATE ADEN ADLAR MUX1 MUX0 MUX DECODER CHANNEL SELECTION VCC 0 ADC DATA REGISTER (ADCH/ADCL) TRIGGER SELECT GAIN SELECTION REFS2..0 BIN IPR 15 ADC CTRL.
If ADC0 or ADC2 is selected as both the positive and negative input to the differential gain amplifier (ADC0-ADC0 or ADC2-ADC2), the remaining offset in the gain stage and conversion circuitry can be measured directly as the result of the conversion. This figure can be subtracted from subsequent conversions with the same gain setting to reduce offset error to below 1 LSW. The on-chip temperature sensor is selected by writing the code “1111” to the MUX3..
ATtiny25/45/85 Figure 20-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles.
ATtiny25/45/85 Figure 20-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion 1 Cycle Number 2 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Prescaler Reset Sample & Hold Prescaler Reset Conversion Complete MUX and REFS Update Figure 20-7.
completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or voltage reference selection values to ADMUX until one ADC clock cycle after ADSC is written. If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings.
ATtiny25/45/85 interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed. Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption. 20.6.
20.6.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 20.6.3 b.
ATtiny25/45/85 Figure 20-10. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 20-11.
Figure 20-12. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code.
ATtiny25/45/85 137). The voltage on the positive pin must always be larger than the voltage on the negative pin or otherwise the voltage difference is saturated to zero. The result is presented in one-sided form, from 0x000 (0d) to 0x3FF (+1023d). The GAIN is either 1x or 20x. 20.7.3 Bipolar Differential Conversion As default the ADC converter operates in the unipolar input mode, but the bipolar input mode can be selected by writting the BIN bit in the ADCSRB to one.
20.7.4 ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR REFS2 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0x07 ADMUX • Bit 7:6,4 – REFS2:REFS0: Voltage Reference Selection Bits These bits select the voltage reference (VREF) for the ADC, as shown in Table 20-2.
ATtiny25/45/85 Table 20-3. Input Channel Selections MUX3..
• Bit 5 – ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. • Bit 4 – ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ATtiny25/45/85 20.7.6 20.7.6.1 ADCL and ADCH – The ADC Data Register ADLAR = 0 Bit 15 14 13 12 11 10 9 8 0x05 – – – – – – ADC9 ADC8 ADCH 0x04 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL Read/Write Initial Value 20.7.6.
• Bits 5 – IPR: Input Polarity Reversal The Input Polarity mode allows software selectable differential input pairs and full 10 bit ADC resolution, in the unipolar input mode, assuming a pre-determined input polarity. If the input polarity is not known it is actually possible to determine the polarity first by using the bipolar input mode (with 9 bit resolution + 1 sign bit ADC measurement). And once determined, set or clear the polarity reversal bit, as needed, for a succeeding 10 bit unipolar measurement.
ATtiny25/45/85 20.8 Temperature Measurement The temperature measurement is based on an on-chip temperature sensor that is coupled to a single ended ADC4 channel. Selecting the ADC4 channel by writing the MUX3..0 bits in ADMUX register to “1111” enables the temperature sensor. The internal 1.1V voltage reference must also be selected for the ADC voltage reference source in the temperature sensor measurement.
21. debugWIRE On-chip Debug System 21.1 Features • • • • • • • • • • 21.
ATtiny25/45/85 When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. • Connecting the RESET pin directly to VCC will not work. • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 21.
22. Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The Program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
ATtiny25/45/85 The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. • The CPU is halted during the Page Write operation. 22.1 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands.
22.1.1 SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory operations. Bit 7 6 5 4 3 2 1 0 0x37 – – – CTPB RFLB PGWRT PGERS SPMEN Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPMCSR • Bits 7:5 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and always read as zero.
ATtiny25/45/85 is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 22.1.3 Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR.
used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 2. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash from unintentional writes. 22.1.5 Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses.
ATtiny25/45/85 23. Memory Programming This section describes the different methods for Programming the ATtiny25/45/85 memories. 23.1 Program And Data Memory Lock Bits The ATtiny25/45/85 provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in Table 23-2. The Lock bits can only be erased to “1” with the Chip Erase command.
23.2 Fuse Bytes The ATtiny25/45/85 has three Fuse bytes. Table 23-4, Table 23-5 and Table61 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 23-3. Fuse Extended Byte Fuse High Byte SELFPRGEN Table 23-4.
ATtiny25/45/85 Table 23-5.
23.4 Calibration Byte Signature area of the ATtiny25/45/85 has one byte of calibration data for the internal RC Oscillator. This byte resides in the high byte of address 0x000. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator. 23.5 Page Size Table 23-6. Device Flash Size Page Size PCWORD No.
ATtiny25/45/85 23.6 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 23-8 on page 153, the pin mapping for SPI programming is listed.
23.6.1 Serial Programming Algorithm When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK. When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See Figure 23-3 and Figure 23-4 for timing details. To program and verify the ATtiny25/45/85 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 23-10): 1.
ATtiny25/45/85 Table 23-9. 23.6.2 Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 4.0 ms tWD_FUSE 4.5 ms Serial Programming Instruction set Table 23-10 on page 155 and Figure 23-2 on page 156 describes the Instruction set. Table 23-10.
Table 23-10. Serial Programming Instruction Set (Continued) Instruction Format Instruction/Operation Byte 1 Byte 2 Byte 3 Byte4 Write Fuse bits $AC $A0 $00 data byte in Write Fuse High bits $AC $A8 $00 data byte in Write Extended Fuse Bits $AC $A4 $00 data byte in Notes: 1. 2. 3. 4. 5. Not all instructions are applicable for all parts. a = address Bits are programmed ‘0’, unprogrammed ‘1’. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .
ATtiny25/45/85 23.6.3 Serial Programming Characteristics Figure 23-3. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Figure 23-4. Serial Programming Timing MOSI tSHOX tOVSH SCK tSLSH tSHSL MISO tSLIV Table 23-11. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 1.8 - 5.
23.7 High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the ATtiny25/45/85. Figure 23-5. High-voltage Serial Programming +11.5 - 12.5V SCI +1.8 - 5.5V PB5 (RESET) VCC PB3 PB2 SDO PB1 SII PB0 SDI GND Table 23-12.
ATtiny25/45/85 23.8 High-voltage Serial Programming Algorithm To program and verify the ATtiny25/45/85 in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in Table 23-15): 23.8.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming mode: 1. Set Prog_enable pins listed in Table 23-13 to “000”, RESET pin and VCC to 0V. 2. Apply 4.5 - 5.5V between VCC and GND.
• Address High byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading. 23.8.3 Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the Program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed. Note: 1.
ATtiny25/45/85 Figure 23-7. High-voltage Serial Programming Waveforms SDI PB0 MSB LSB SII PB1 MSB LSB SDO PB2 MSB SCI PB3 23.8.5 0 LSB 1 2 3 4 5 6 7 8 9 10 Programming the EEPROM The EEPROM is organized in pages, see Table 23-11 on page 157. When programming the EEPROM, the data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM Data memory is as follows (refer to Table 23-15): 1.
Table 23-15. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 Instruction Format Instruction Chip Erase Load “Write Flash” Command Load Flash Page Buffer Instr.1/5 Instr.2/6 Instr.3 SDI 0_1000_0000_00 0_0000_0000_00 0_0000_0000_00 SII 0_0100_1100_00 0_0110_0100_00 0_0110_1100_00 SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx SDI 0_0001_0000_00 SII 0_0100_1100_00 Instr.4 Wait after Instr.3 until SDO goes high for the Chip Erase cycle to finish.
ATtiny25/45/85 Table 23-15. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued) Instruction Format Instruction Write EEPROM Byte Instr.1/5 Instr.2/6 Instr.3 Instr.
Table 23-15. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued) Instruction Format Instruction Instr.1/5 Instr.2/6 Instr.3 Instr.
ATtiny25/45/85 24. Electrical Characteristics 24.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)(1) (Continued) Symbol Parameter Condition Power Supply Current ICC Power-down mode Min. Typ. Max. Units Active 1MHz, VCC = 2V 0.55 mA Active 4MHz, VCC = 3V 2.5 mA Active 8MHz, VCC = 5V 8 mA Idle 1MHz, VCC = 2V 0.2 mA Idle 4MHz, VCC = 3V 0.6 mA Idle 8MHz, VCC = 5V 2 mA WDT enabled, VCC = 3V 10 µA WDT disabled, VCC = 3V 2 µA Notes: 1.
ATtiny25/45/85 24.4 External Clock Drive Table 24-1. External Clock Drive VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Min. Max. Min. Max. Min. Max. Units 0 4 0 10 0 20 MHz Symbol Parameter 1/tCLCL Clock Frequency tCLCL Clock Period 250 100 50 ns tCHCX High Time 100 40 20 ns tCLCX Low Time 100 40 20 ns tCLCH Rise Time 2.0 1.6 0.5 µs tCHCL Fall Time 2.0 1.6 0.5 µs ∆tCLCL Change in period from one clock cycle to the next 2 2 2 % 24.
24.6 ADC Characteristics – Preliminary Data Table 24-2. Symbol ADC Characteristics, Single Ended Channels. -40°C - 85°C Parameter Resolution Min(1) Single Ended Conversion Units 10 Bits LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1 MHz 3 LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 1.5 LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 2.
ATtiny25/45/85 25. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled.
Figure 25-2. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 14 5.5 V 12 5.0 V ICC (mA) 10 4.5 V 8 4.0V 6 3.3V 4 2.7V 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 25-3. Active Supply Current vs. VCC (Internal RC oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs.
ATtiny25/45/85 Figure 25-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 1,6 25 ˚C 85 ˚C -40 ˚C 1,4 ICC (mA) 1,2 1 0,8 0,6 0,4 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 25-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs.
Figure 25-6. Idle Supply Current vs. low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 0,25 5.5 V 5.0 V 0,2 4.5 V ICC (mA) 4.0 V 0,15 3.3 V 2.7 V 0,1 1.8 V 0,05 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 25-7. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 4 5.5 V 3 5.0 V 2,5 4.5 V ICC (mA) 3,5 2 4.0V 1,5 3.3V 1 2.7V 0,5 1.
ATtiny25/45/85 Figure 25-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)I IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 1,8 85 ˚C 1,6 25 ˚C 1,4 -40 ˚C ICC (mA) 1,2 1 0,8 0,6 0,4 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 25-9. Idle Supply Current vs. VCC (Internal RC Oscilllator, 1 MHz) IDLE SUPPLY CURRENT vs.
Figure 25-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 128 kHz 0,1 0,09 -40 ˚C 25 ˚C 0,08 85 ˚C ICC (mA) 0,07 0,06 0,05 0,04 0,03 0,02 0,01 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 25.2 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode.
ATtiny25/45/85 It is possible to calculate the typical current consumption based on the numbers from Table 2 for other VCC and frequency settings than listed in Table 1. 25.2.0.1 Example 1 Calculate the expected current consumption in idle mode with USI, TIMER0, and ADC enabled at VCC = 2.0V and F = 1MHz. From Table 25-4 on page 171, third column, we see that we need to add 6.4% for the USI, 21.4% for the ADC, and 7.3% for the TIMER0 module.
Figure 25-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 10 -40 ˚C 85 ˚C 25 ˚C 9 8 ICC (uA) 7 6 5 4 3 2 1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 25.4 Pin Pull-up Figure 25-13. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 1.
ATtiny25/45/85 Figure 25-14. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 80 70 60 IOP (uA) 50 40 30 20 25 ˚C 85 ˚C 10 -40 ˚C 0 0 0,5 1 1,5 2 2,5 3 VOP (V) Figure 25-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs.
Figure 25-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 1.8V 40 35 IRESET(uA) 30 25 20 15 10 25 ˚C -40 ˚C 85 ˚C 5 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VRESET (V) Figure 25-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC =2.
ATtiny25/45/85 Figure 25-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 5V 120 100 IRESET(uA) 80 60 40 25 ˚C -40 ˚C 85 ˚C 20 0 0 1 2 3 4 5 6 VRESET(V) 25.5 Pin Driver Strength Figure 25-19. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs.
Figure 25-20. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 0,6 85 0,5 25 VOL (V) 0,4 -40 0,3 0,2 0,1 0 0 5 10 15 20 25 IOL (mA) Figure 25-21. I/O Pin Output Voltage vs. Source Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs.
ATtiny25/45/85 Figure 25-22. I/O Pin Output Voltage vs. Source Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5,1 5 VOH (V) 4,9 4,8 4,7 4,6 -40 25 4,5 85 4,4 0 5 10 15 20 25 IOH (mA) 25.6 Pin Threshold and Hysteresis Figure 25-23. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’) I/O PIN INPUT THRESHOLD VOLTAGE vs.
Figure 25-24. I/O Pin Input Threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 3 85 ˚C 25 ˚C 2,5 Threshold (V) -40 ˚C 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 25-25. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs.
ATtiny25/45/85 Figure 25-26. Reset Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2,5 85 ˚C 25 ˚C Threshold (V) 2 -40 ˚C 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 25-27. Reset Input Threshold Voltage vs, VCC (VIL, IO Pin Read as ‘0’) RESET INPUT THRESHOLD VOLTAGE vs.
Figure 25-28. Reset Pin Input Hysteresis vs. VCC RESET PIN INPUT HYSTERESIS vs. VCC 0,045 85 ˚C 25 ˚C -40 ˚C Input Hysteresis (mV) 0,04 0,035 0,03 0,025 0,02 0,015 0,01 0,005 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 25.7 BOD Threshold and Analog Comparator Offset Figure 25-29. BOF Threshold vs, Temperature (BOD Level is 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL is 4.
ATtiny25/45/85 Figure 25-30. BOD Threshold vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL is 2.7V 2,8 Threshold (V) 2,75 2,7 Rising VCC 2,65 2,6 Falling VCC 2,55 2,5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) Figure 25-31. BOD Threshold vs. Temperature (BOD Level is 1.8V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL is 1.
25.8 Internal Oscillator Speed Figure 25-32. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. VCC 0,128 0,126 FRC (MHz) 0,124 -40 ˚C 0,122 25 ˚C 0,12 0,118 0,116 0,114 85 ˚C 0,112 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 25-33. Watchdog Oscillator Frequency vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 0,128 0,126 FRC (MHz) 0,124 0,122 0,12 0,118 1.8 V 2.7 V 3.3 V 4.0 V 5.
ATtiny25/45/85 Figure 25-34. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. VCC 8,2 85 ˚C 8,1 FRC (MHz) 8 25 ˚C 7,9 7,8 -40 ˚C 7,7 7,6 7,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 25-35. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8,15 3.0 V 8,1 8,05 5.
Figure 25-36. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 18 85 ˚C 25 ˚C 16 14 -40 ˚C FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) Figure 25-37. Calibrated 1.6 MHz RC Oscillator Frequency vs. VCC CALIBRATED 1.6 MHz RC OSCILLATOR FREQUENCY vs.
ATtiny25/45/85 Figure 25-38. Calibrated 1.6 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 1.6MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1,64 3.0 V 1,62 5.0 V FRC (MHz) 1,6 1,58 1,56 1,54 1,52 1,5 -60 -40 -20 0 20 40 60 80 100 Temperature Figure 25-39. Calibrated 1.6 MHz RC Oscillator Frequency vs. OSCCAL Value CALIBRATED 1.6 MHz RC OSCILLATOR FREQUENCY vs.
25.9 Current Consumption of Peripheral Units Figure 25-40. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 35 -40 ˚C 25 ˚C 85 ˚C 30 ICC (uA) 25 20 15 10 5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 25-41. ADC Current vs, VCC (AREF = AVCC) ADC CURRENT vs.
ATtiny25/45/85 Figure 25-42. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC ICC (uA) 70 60 -40 ˚C 25 ˚C 50 85 ˚C 40 30 20 10 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 25-43. Programming Current vs. VCC PROGRAMMING CURRENT vs.
25.10 Current Consumption in Reset and Reset Pulsewidth Figure 25-44. Reset Supply Current vs, VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. VCC 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP ICC (mA) 0,16 0,14 5.5 V 0,12 5.0 V 4.5 V 0,1 4.0 V 0,08 3.3 V 0,06 2.7 V 0,04 1.8 V 0,02 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 25-45. Reset Supply Current vs.
ATtiny25/45/85 Figure 25-46. Minimum Reset Pulse Width vs, VCC MINIMUM RESET PULSE WIDTH vs.
26.
ATtiny25/45/85 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them.
27.
ATtiny25/45/85 Mnemonics Operands Description Operation Flags #Clocks ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..
28. Ordering Information 28.1 ATtiny25 Speed (MHz)(3) 10 20 Notes: Power Supply Ordering Code Package(1)(2) 1.8 - 5.5V ATtiny25V-10PI ATtiny25V-10PU ATtiny25V-10SI ATtiny25V-10SU ATtiny25V-10MU 8P3 8P3 8S2 8S2 20M1 Industrial (-40°C to 85°C) 2.7 - 5.5V ATtiny25-20PI ATtiny25-20PU ATtiny25-20SI ATtiny25-20SU ATtiny25-20MU 8P3 8P3 8S2 8S2 20M1 Industrial (-40°C to 85°C) Operational Range 1. This device can also be supplied in wafer form.
ATtiny25/45/85 28.2 ATtiny45 Speed (MHz)(3) 10 20 Notes: Power Supply Ordering Code Package(1)(2) 1.8 - 5.5V ATtiny45V-10PI ATtiny45V-10PU ATtiny45V-10SI ATtiny45V-10SU ATtiny45V-10MU 8P3 8P3 8S2 8S2 20M1 Industrial (-40°C to 85°C) 2.7 - 5.5V ATtiny45-20PI ATtiny45-20PU ATtiny45-20SI ATtiny45-20SU ATtiny45-20MU 8P3 8P3 8S2 8S2 20M1 Industrial (-40°C to 85°C) Operational Range 1. This device can also be supplied in wafer form.
28.3 ATtiny85 Speed (MHz)(3) 10 20 Notes: Power Supply Ordering Code Package(1)(2) 1.8 - 5.5V ATtiny85V-10PI ATtiny85V-10PU ATtiny85V-10SI ATtiny85V-10SU ATtiny85V-10MU 8P3 8P3 8S2 8S2 20M1 Industrial (-40°C to 85°C) 2.7 - 5.5V ATtiny85-20PI ATtiny85-20PU ATtiny85-20SI ATtiny85-20SU ATtiny85-20MU 8P3 8P3 8S2 8S2 20M1 Industrial (-40°C to 85°C) Operational Range 1. This device can also be supplied in wafer form.
ATtiny25/45/85 29. Packaging Information 29.1 8P3 E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A SYMBOL MIN NOM A b2 b3 b 4 PLCS Side View L 0.210 NOTE 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 0.150 2 e 3 3 0.100 BSC eA L Notes: MAX 0.300 BSC 0.115 0.
29.2 8S2 C 1 E E1 L N Top View ∅ End View e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D Side View NOM MAX NOTE 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 5 C 0.15 0.35 5 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 ∅ 0˚ e Notes: 1. 2. 3. 4. 5. MIN A 2, 3 8˚ 1.27 BSC 4 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs are not included.
ATtiny25/45/85 29.3 20M1 D 1 Pin 1 ID 2 SIDE VIEW E 3 TOP VIEW A2 D2 A1 A 0.08 1 2 Pin #1 Notch (0.20 R) 3 COMMON DIMENSIONS (Unit of Measure = mm) E2 b L e BOTTOM VIEW SYMBOL MIN A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 b 0.18 D D2 E2 L MAX NOTE 0.23 0.30 4.00 BSC 2.45 2.60 2.75 4.00 BSC 2.45 e Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. NOM 0.20 REF E Note: C 2.60 2.75 0.50 BSC 0.35 0.40 0.
30. Errata 30.1 Errata ATtiny25 The revision letter in this section refers to the revision of the ATtiny25 device. 30.1.1 Rev A and B Not sampled.
ATtiny25/45/85 30.2 Errata ATtiny45 The revision letter in this section refers to the revision of the ATtiny45 device. 30.2.1 Rev A • • • • • Too high power down power consumption DebugWIRE looses communication when single stepping into interrupts PLL not locking EEPROM read from application code does not work in Lock Bit Mode 3 EEPROM write may fail with VCC below 2.0 volts 1. Too high power down power consumption Three situations will lead to a too high power down power consumption.
5. EEPROM Write may fail with VCC below 2.0 volts When VCC is below 2.0 volts, EEPROM write may fail. Problem Fix/Work around Do not write the EEPROM when VCC is below 2.0 volts 30.2.2 Rev B and C • • • • PLL not locking EEPROM read from application code does not work in Lock Bit Mode 3 EEPROM write may fail with VCC below 2.0 volts Timer Counter 1 PWM output generation on OC1B- XOC1B does not work correctly 1. PLL not locking When at frequencies below 6.
ATtiny25/45/85 30.3 Errata ATtiny85 The revision letter in this section refers to the revision of the ATtiny85 device. 30.3.1 Rev A No known errata.
31. Datasheet Revision History 31.1 Rev. 2586D-02/06 1. 2. 3. 4. 5. 6. 7. 8. 9. 31.2 Rev. 2586C-06/05 1. 2. 3. 4. 5. 6. 31.3 2. 3. 4. 5. 6. 7. 8. 9. CLKI added, instances of EEMWE/EEWE renamed EEMPE/EEPE, removed some TBD. Removed “Preliminary Description” from ”Temperature Measurement” on page 141. Updated ”Features” on page 1. Updated Figure 1-1 on page 2 and Figure 9-1 on page 36.
ATtiny25/45/85 Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1 Disclaimer .................................................................................................................2 2 Overview ................................................................................................... 3 2.
7.10 System Clock Prescaler .......................................................................................30 8 Power Management and Sleep Modes ................................................. 32 8.1 Idle Mode ................................................................................................................33 8.2 ADC Noise Reduction Mode ..................................................................................33 8.3 Power-down Mode .........................................
ATtiny25/45/85 16 8-bit Timer/Counter1 in ATtiny15 Mode ............................................... 96 16.1 Timer/Counter1 Prescaler ....................................................................................96 16.2 Timer/Counter1 ....................................................................................................96 17 Dead Time Generator ........................................................................... 106 18 USI – Universal Serial Interface .........................
23.5 Page Size ...........................................................................................................152 23.6 Serial Downloading ............................................................................................153 23.7 High-voltage Serial Programming .......................................................................158 23.8 High-voltage Serial Programming Algorithm ......................................................159 23.
ATtiny25/45/85 30.1 Errata ATtiny25 ..................................................................................................204 30.2 Errata ATtiny45 ..................................................................................................205 30.3 Errata ATtiny85 ..................................................................................................207 31 Datasheet Revision History ................................................................ 208 31.1 Rev. 2586D-02/06 ......
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