Datasheet

79
8006H–AVR–10/09
ATtiny24/44/84
Figure 11-8. Timer/Counter Timing Diagram, no Prescaling
Figure 11-9 on page 79 shows the same timing data, but with the prescaler enabled.
Figure 11-9. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
Figure 11-10 on page 79 shows the setting of OCF0B in all modes and OCF0A in all modes
except CTC mode and PWM mode, where OCR0A is TOP.
Figure 11-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f
clk_I/O
/8)
Figure 11-11 on page 80 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode
and fast PWM mode where OCR0A is TOP.
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)