Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-Volatile Program and Data Memories – 2/4/8K Bytes of In-System Programmable Program Memory Flash • Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes of In-System Programmable EEPROM • Endurance: 100,000 Write/Erase Cycles – 128/256/512 Bytes of Inter
1. Pin Configurations Figure 1-1. Pinout ATtiny24/44/84 PDIP/SOIC VCC (PCINT8/XTAL1/CLKI) PB0 (PCINT9/XTAL2) PB1 (PCINT11/RESET/dW) PB3 (PCINT10/INT0/OC0A/CKOUT) PB2 (PCINT7/ICP/OC0B/ADC7) PA7 (PCINT6/OC1A/SDA/MOSI/DI/ADC6) PA6 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND PA0 (ADC0/AREF/PCINT0) PA1 (ADC1/AIN0/PCINT1) PA2 (ADC2/AIN1/PCINT2) PA3 (ADC3/T0/PCINT3) PA4 (ADC4/USCK/SCL/T1/PCINT4) PA5 (ADC5/DO/MISO/OC1B/PCINT5) NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect 1.1 1.1.
ATtiny24/44/84 Port B also serves the functions of various special features of the ATtiny24/44/84 as listed in Section 10.2 “Alternate Port Functions” on page 58. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 20-4 on page 177. Shorter pulses are not guaranteed to generate a reset.
2. Overview ATtiny24/44/84 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24/44/84 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1.
ATtiny24/44/84 The ATtiny24/44/84 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32 general purpose working registers, an 8-bit Timer/Counter with two PWM channels, a 16-bit timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC, programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable Watchdog Timer with internal oscillator, int
3. About 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation.
ATtiny24/44/84 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 Architectural Overview Figure 4-1.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
ATtiny24/44/84 The Status Register is neither automatically stored when entering an interrupt routine, nor restored when returning from an interrupt. This must be handled by software. 4.3.1 SREG – AVR Status Register Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled.
4.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATtiny24/44/84 Figure 4-3. The X-, Y-, and Z-registers 15 X-register XH XL 7 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.
4.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept.
ATtiny24/44/84 priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in the following example. Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ Note: 4.7.
ATtiny24/44/84 5. Memories This section describes the different memories in the ATtiny24/44/84. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny24/44/84 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 5.1 In-System Re-programmable Flash Program Memory The ATtiny24/44/84 contains 2/4/8K byte On-chip In-System Reprogrammable Flash memory for program storage.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of internal data SRAM in the ATtiny24/44/84 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10. Figure 5-2.
ATtiny24/44/84 5.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 5-1 on page 22. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down.
The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on page 30. 5.3.6 Program Examples The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATtiny24/44/84 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 5.4 I/O Memory The I/O space definition of the ATtiny24/44/84 is shown in “Register Summary” on page 213. All ATtiny24/44/84 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space.
ATtiny24/44/84 5.5.2 EEARL – EEPROM Address Register Bit 7 6 5 4 3 2 1 0 0x1E (0x3E) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X EEARL • Bit 7 – EEAR7: EEPROM Address This is the most significant EEPROM address bit of ATtiny44. In devices with less EEPROM, i.e. ATtiny24, this bit is reserved and will always read zero.
old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 5-1. Table 5-1. EEPROM Programming Mode Bits and Programming Times EEPM1 EEPM0 Programming Time Operation 0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Reserved for future use When EEPE is set any write to EEPMn will be ignored.
ATtiny24/44/84 5.5.5 GPIOR2 – General Purpose I/O Register 2 Bit 5.5.6 6 5 4 3 2 1 0 MSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 LSB 5 4 3 2 1 GPIOR2 GPIOR1 – General Purpose I/O Register 1 Bit 5.5.
6. Clock System Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 33. Figure 6-1.
ATtiny24/44/84 6.1.2 I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. 6.1.3 Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 6.1.
6.2.1 External Clock To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-2 on page 26. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 6-2. External Clock Drive Configuration EXTERNAL CLOCK SIGNAL CLKI GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-3. Table 6-3. Start-up Times for the External Clock Selection SUT1..
ATtiny24/44/84 ibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table 20-2 on page 176. By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on page 30, it is possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is shown as User calibration in Table 20-2 on page 176.
6.2.4 Low-Frequency Crystal Oscillator To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystal oscillator must be selected by setting CKSEL fuses to ‘0110’. The crystal should be connected as shown in Figure 6-3. To find suitable capacitors please consult the manufacturer’s datasheet. For this oscillator start-up times can be set with the SUT fuses, as shown in Table 6-7. Table 6-7. Start-up Times for the Low-Frequency Crystal Oscillator Clock Selection SUT1..
ATtiny24/44/84 Table 6-9. Crystal Oscillator Operating Modes CKSEL3..1 Frequency Range (MHz) Recommended C1 and C2 Value (pF) 0.4 - 0.9 – 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 12 - 22 100 Notes: (1) 1. This option should not be used with crystals, only with ceramic resonators. The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by fuses CKSEL3..1 as shown in Table 6-9.
6.2.6 Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is therefore the Internal Oscillator running at 8.0 MHz with longest start-up time and an initial system clock prescaling of 8, resulting in 1.0 MHz system clock. This default setting ensures that all users can make their desired clock source setting using an in-system or high-voltage programmer.
ATtiny24/44/84 The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the Factory calibrated frequency as specified in Table 20-2 on page 176. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 202 on page 176.
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”.
ATtiny24/44/84 7. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.
the Analog Comparator can be powered down by setting the ACD bit in “ACSR – Analog Comparator Control and Status Register” on page 130. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.1.2 ADC Noise Reduction Mode When the SM1..
ATtiny24/44/84 7.2.1 Limitations BOD disable functionality has been implemented in the following devices, only: • ATtiny24, revision E, and newer • ATtiny44, revision D, and newer • ATtiny84, revision B, and newer Revisions are marked on the device package and can be located as follows: • Bottom side of packages 14P3 and 14S1 • Top side of package 20M1 7.
7.4.3 Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. See “Brown-out Detection” on page 41 and “Software BOD Disable” on page 34 for details on how to configure the Brown-out Detector. 7.4.
ATtiny24/44/84 both BODS and BODSE must be set to one. Second, within four clock cycles, BODS must be set to one and BODSE must be set to zero. The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles. In devices where Sleeping BOD has not been implemented this bit is unused and will always read zero.
• Bit 2 – PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. • Bit 1 – PRUSI: Power Reduction USI Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI again, the USI should be re initialized to ensure proper operation. • Bit 0 – PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC.
ATtiny24/44/84 8. System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 8-1 shows the reset logic.
8.2 Reset Sources The ATtiny24/44/84 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length when RESET function is enabled. • Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. • Brown-out Reset.
ATtiny24/44/84 8.2.2 External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see “System and Reset Characteristics” on page 177) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after the Time-out period – tTOUT – has expired. Figure 8-4.
8.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. See “Watchdog Timer” on page 42 for details on operation of the Watchdog Timer. Figure 8-6. Watchdog Reset During Operation CC CK 8.3 Internal Voltage Reference ATtiny24/44/84 features an internal bandgap reference.
ATtiny24/44/84 The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down. To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in Table 8-1 See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 43 for details. Table 8-1.
8.4.1.2 Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: 1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2.
ATtiny24/44/84 8.5 8.5.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 7 6 5 4 3 2 1 0 0x34 (0x54) – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 8-2. Watchdog Timer Configuration WDE WDIE Watchdog Timer State Action on Time-out 0 0 Stopped None 0 1 Running Interrupt 1 0 Running Reset 1 1 Running Interrupt • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled.
ATtiny24/44/84 • Bits 5, 2..0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1, and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 8-3. Table 8-3. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.
9. Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny24/44/84. For a general explanation of the AVR interrupt handling, see “Reset and Interrupt Handling” on page 12. 9.1 Interrupt Vectors The interrupt vectors of ATtiny24/44/84 are described in Table 9-1 below. Table 9-1. Reset and Interrupt Vectors Vector No.
ATtiny24/44/84 Address Labels Code Comments 0x0000 rjmp RESET ; Reset Handler 0x0001 rjmp INT0 ; IRQ0 Handler 0x0002 rjmp PCINT0 ; PCINT0 Handler 0x0003 rjmp PCINT1 ; PCINT1 Handler 0x0004 rjmp WDT ; Watchdog Interrupt Handler 0x0005 rjmp TIM1_CAPT ; Timer1 Capture Handler 0x0006 rjmp TIM1_COMPA ; Timer1 Compare A Handler 0x0007 rjmp TIM1_COMPB ; Timer1 Compare B Handler 0x0008 rjmp TIM1_OVF ; Timer1 Overflow Handler 0x0009 rjmp TIM0_COMPA ; Timer0 Compare A Handler
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL fuses, as described in “Clock System” on page 24.
ATtiny24/44/84 9.3 9.3.1 Register Description MCUCR – MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 4– PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register. 9.3.
ATtiny24/44/84 9.3.5 PCMSK0 – Pin Change Mask Register 0 Bit 7 6 5 4 3 2 1 0 0x12 (0x32) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK0 • Bits 7..0 – PCINT7..0: Pin Change Enable Mask 7..0 Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..
10. I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability.
ATtiny24/44/84 10.1 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx WPx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 10.1.
10.1.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 10.1.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
ATtiny24/44/84 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge.
C Code Example unsigned char i; ... /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTA = (1<
ATtiny24/44/84 Figure 10-5.
Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 10-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
ATtiny24/44/84 10.2.1 Alternate Functions of Port A The Port A pins with alternate function are shown in Table 10-3. Table 10-3.
• Port A, Bit 1 – ADC1/AIN0/PCINT1 • ADC1: Analog to Digital Converter, Channel 1. • AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pullup switched off to avoid the digital port function from interfering with the function of the Analog Comparator. • PCINT1: Pin Change Interrupt source 1. The PA1 pin can serve as an external interrupt source for pin change interrupt 0. • Port A, Bit 2 – ADC2/AIN1/PCINT2 • ADC2: Analog to Digital Converter, Channel 2.
ATtiny24/44/84 • Port A, Bit 6 – ADC6/DI/SDA/MOSI/OC1A/PCINT6 • ADC6: Analog to Digital Converter, Channel 6. • SDA: Two-wire mode Serial Interface Data. • DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions, so pin must be configure as an input for DI function. • MOSI: Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDA6.
Table 10-5.
ATtiny24/44/84 10.2.2 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10-7. Table 10-7.
• Port B, Bit 3 – RESET/dW/PCINT11 • RESET: External Reset input is active low and enabled by unprogramming (“1”) the RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin. • dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated.
ATtiny24/44/84 Table 10-9. Signal Name Overriding Signals for Alternate Functions in PB1..PB0 PB1/XTAL2/PCINT9 PB0/XTAL1/PCINT8 (1) EXT_CLOCK (2) + EXT_OSC(1) PUOE EXT_OSC PUOV 0 0 DDOE EXT_OSC(1) EXT_CLOCK(2) + EXT_OSC(1) DDOV 0 0 PVOE EXT_OSC PVOV 0 PTOE 0 (1) EXT_CLOCK(2) + EXT_OSC(1) 0 0 (1) 10.3 10.3.
10.3.4 PINA – Port A Input Pins Bit 10.3.5 10.3.6 10.3.
ATtiny24/44/84 11. 8-bit Timer/Counter0 with PWM 11.1 Features • • • • • • • 11.2 Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support.
11.2.1 Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in Figure 11-1) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin.
ATtiny24/44/84 Figure 11-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count clear TCNTn Control Logic clkTn Edge Detector Tn direction ( From Prescaler ) bottom top Signal description (internal signals): count direction clear clkTn top bottom Increment or decrement TCNT0 by 1. Select between increment and decrement. Clear TCNT0 (set all bits to zero). Timer/Counter clock, referred to as clkT0 in the following. Signalize that TCNT0 has reached maximum value.
Figure 11-3 shows a block diagram of the Output Compare unit. Figure 11-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
ATtiny24/44/84 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (0x) strobe bits in Normal mode.
The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation, see “Register Description” on page 80 11.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes.
ATtiny24/44/84 The timing diagram for the CTC mode is shown in Figure 11-5 on page 75. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 11-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag.
for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 11-6 on page 76.
ATtiny24/44/84 in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of 0 = fclk_I/O/2 when OCR0A is set to zero.
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM.
ATtiny24/44/84 Figure 11-8. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 11-9 on page 79 shows the same timing data, but with the prescaler enabled. Figure 11-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 11-10 on page 79 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP.
Figure 11-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP OCRnx OCFnx 11.9 11.9.
ATtiny24/44/84 Table 11-3. Compare Output Mode, Fast PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected WGM02 = 1: Toggle OC0A on Compare Match 1 0 Clear OC0A on Compare Match Set OC0A at BOTTOM (non-inverting mode) 1 1 Set OC0A on Compare Match Clear OC0A at BOTTOM (inverting mode) Note: Description 1. A special case occurs when OCR0A equals TOP and COM0A1 is set.
Table 11-6 shows COM0B1:0 bit functionality when WGM02:0 bits are set to fast PWM mode. Table 11-6. Compare Output Mode, Fast PWM Mode(1) COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match, set OC0B at BOTTOM (non-inverting mode) 1 1 Set OC0B on Compare Match, clear OC0B at BOTTOM (inverting mode) Note: Description 1. A special case occurs when OCR0B equals TOP and COM0B1 is set.
ATtiny24/44/84 Table 11-8. Timer/Counter Mode of Operation TOP Update of OCRx at TOV Flag Set on(1) 0 Normal 0xFF Immediate MAX 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 0 1 0 CTC OCRA Immediate MAX 3 0 1 1 Fast PWM 0xFF BOTTOM MAX 4 1 0 0 Reserved – – – 5 1 0 1 PWM, Phase Correct OCRA TOP BOTTOM 6 1 1 0 Reserved – – – 7 1 1 1 Fast PWM OCRA BOTTOM TOP Mode WGM02 WGM01 WGM00 0 0 0 1 0 2 Note: 11.9.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the “TCCR0A – Timer/Counter Control Register A” on page 80. • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter.
ATtiny24/44/84 11.9.5 OCR0B – Output Compare Register B Bit 7 6 5 0x3C (0x5C) 4 3 2 1 0 OCR0B[7:0] OCR0B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0B pin. 11.9.
the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed. • Bit 1– OCF0A: Output Compare Flag 0 A The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag.
ATtiny24/44/84 12. 16-bit Timer/Counter1 12.1 Features • • • • • • • • • • • 12.2 True 16-bit Design (i.e.
Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. 12.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers.
ATtiny24/44/84 12.2.3 Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of 16-bit AVR Timer/Counters. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: • All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers. • Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers. • Interrupt Vectors.
Signal description (internal signals): Count Direction Clear clkT1 TOP BOTTOM Increment or decrement TCNT1 by 1. Select between increment and decrement. Clear TCNT1 (set all bits to zero). Timer/Counter clock. Signalize that TCNT1 has reached maximum value. Signalize that TCNT1 has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits.
ATtiny24/44/84 Figure 12-3. Input Capture Unit Block Diagram DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) WRITE ICRnL (8-bit) TCNTnH (8-bit) ICRn (16-bit Register) ACO* Analog Comparator ACIC* TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.
Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 13-1 on page 115). The edge detector is also identical.
ATtiny24/44/84 (WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (“Modes of Operation” on page 96). A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator.
ister since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Register in the same system clock cycle.
ATtiny24/44/84 Figure 12-5. Compare Match Output Unit, Schematic (non-PWM Mode) COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
12.8 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATtiny24/44/84 Figure 12-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
ATtiny24/44/84 value when the counter is running with none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location to be written anytime.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
ATtiny24/44/84 changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value.
the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction.
ATtiny24/44/84 Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
Figure 12-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 12-12 on page 104 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
ATtiny24/44/84 Figure 12-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value 12.10 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus.
Assembly Code Examples ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Examples unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ... Note: See “Code Examples” on page 6. The assembly code example returns the TCNT1 value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations.
ATtiny24/44/84 C Code Example unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: See “Code Examples” on page 6. The assembly code example returns the TCNT1 value in the r17:r16 register pair. The following code examples show how to do an atomic write of the TCNT1 Register contents.
C Code Example void TIM16_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; } Note: See “Code Examples” on page 6. The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1. 12.10.
ATtiny24/44/84 Table 12-2. Compare Output Mode, non-PWM COM1A1/COM1B1 COM1A0/COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 Toggle OC1A/OC1B on Compare Match. 1 0 Clear OC1A/OC1B on Compare Match (Set output to low level). 1 1 Set OC1A/OC1B on Compare Match (Set output to high level). Table 12-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 12-3.
• Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 12-5 on page 110. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (“Modes of Operation” on page 96). Table 12-5.
ATtiny24/44/84 When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled.
FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. • Bit 5..0 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when the register is written.
ATtiny24/44/84 12.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit 7 6 5 4 3 0x25 (0x45) ICR1[15:8] 0x24 (0x44) ICR1[7:0] 2 1 0 ICR1H ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value.
12.11.9 TIFR1 – Timer/Counter Interrupt Flag Register 1 Bit 0x0B (0x2B) 7 – 6 – 5 ICF1 4 – 3 – 2 1 OCF1B OCF1A 0 TOV1 TIFR1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7,6,4,3 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when the register is written. • Bit 5– ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin.
ATtiny24/44/84 13. Timer/Counter Prescaler Timer/Counter0 and Timer/Counter1 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counters. Tn is used as a general name, n = 0, 1. The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 13-2. Prescaler for Timer/Counter0 clk I/O Clear PSR10 T0 Synchronization clkT0 Note: 13.3 13.3.1 1.
ATtiny24/44/84 14. USI – Universal Serial Interface 14.1 Features • • • • • • 14.2 Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wakeup from Idle Mode In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode Two-wire Start Condition Detector with Interrupt Capability Overview The Universal Serial Interface (USI), provides the basic hardware resources needed for serial communication.
the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. The 4-bit counter can be both read and written via the data bus, and it can generate an overflow interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same clock source.
ATtiny24/44/84 Figure 14-3. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The three-wire mode timing is shown in Figure 14-3 At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
SPITransfer_loop: out USICR,r17 in r16, USISR sbrs r16, USIOIF rjmp SPITransfer_loop in r16,USIDR ret The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRA. The value stored in register r16 prior to the function is called is transferred to the slave device, and when the transfer is completed the data received from the slave is stored back into the register r16.
ATtiny24/44/84 14.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<
Figure 14-4. Two-wire Mode Operation, Simplified Diagram VCC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL HOLD SCL Two-wire Clock Control Unit SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL PORTxn MASTER The data direction is not given by the physical layer. A protocol, like the one used by the TWIbus, must be implemented to control the data flow. Figure 14-5.
ATtiny24/44/84 3. The master set the first bit to be transferred and releases the SCL line (C). The slave samples the data and shifts it into the USI Data Register at the positive edge of the SCL clock. 4. After eight bits containing slave address and data direction (read or write) have been transferred, the slave counter overflows and the SCL line is forced low (D). If the slave is not the one the master has addressed, it releases the SCL line and waits for a new start condition. 5.
14.4 Alternative USI Usage The flexible design of the USI allows it to be used for other tasks when serial communication is not needed. Below are some examples. 14.4.1 Half-Duplex Asynchronous Data Transfer Using the USI Data Register in three-wire mode it is possible to implement a more compact and higher performance UART than by software, only. 14.4.2 4-Bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt.
ATtiny24/44/84 14.5.2 USIBR – USI Data Buffer Bit 7 6 5 4 3 2 1 0 0x10 (0x30) MSB LSB Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 USIBR Instead of reading data from the USI Data Register the USI Buffer Register can be used. This makes controlling the USI less time critical and gives the CPU more time to handle other program tasks. USI flags as set similarly as when reading the USIDR register.
The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe bits. The clock source depends on the setting of the USICS1:0 bits. For external clock operation a special feature is added that allows the clock to be generated by writing to the USITC strobe bit. This feature is enabled by choosing an external clock source (USICS1 = 1) and writing a one to the USICLK bit.
ATtiny24/44/84 Table 14-1. Relationship between USIWM1:0 and USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operate as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORTA register. However, the corresponding DDRA bit still controls the data direction. When the port pin is set as input the pin pull-up is controlled by the PORTA bit.
Table 14-2 shows the relationship between the USICS1:0 and USICLK setting and clock source used for the USI Data Register and the 4-bit counter. Table 14-2.
ATtiny24/44/84 15. Analog Comparator The analog comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle.
Table 15-1. 15.2 15.2.1 Analog Comparator Multiplexed Input (Continued) ACME ADEN MUX4..
ATtiny24/44/84 between the Analog Comparator and the input capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture inter-rupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set. • Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 15-2. Table 15-2.
16. Analog to Digital Converter 16.1 Features • • • • • • • • • • • • • • • • • 16.2 10-bit Resolution 1.0 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 13µs Conversion Time 15 kSPS at Maximum Resolution Eight Multiplexed Single Ended Input Channels Twelve Differential Input Channels with Selectable Gain (1x, 20x) Temperature Sensor Input Channel Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range 1.
ATtiny24/44/84 Figure 16-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS2...ADTS0 AREF VCC INTERNAL REFERENCE 1.1V TRIGGER SELECT ADC[9:0] ADPS1 ADPS0 ADPS2 ADIF ADSC ADATE ADEN ADLAR MUX4...MUX0 0 ADC DATA REGISTER (ADCH/ADCL) MUX DECODER CHANNEL SELECTION REFS1..REFS0 BIN 15 ADC CTRL. & STATUS A REGISTER (ADCSRA) ADC MULTIPLEXER SELECT (ADMUX) PRESCALER START GAIN SELECTION ADC CTRL.
If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input pair by the selected gain factor, 1x or 20x, according to the setting of the MUX0 bit in ADMUX. This amplified value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether. The offset of the differential channels can be measure by selecting the same input for both negative and positive input.
ATtiny24/44/84 Figure 16-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
The ADC module contains a prescaler, as illustrated in Figure 16-3 on page 135, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
ATtiny24/44/84 When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in Figure 16-6 below. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. Figure 16-6.
For a summary of conversion times, see Table 16-1. Table 16-1. ADC Conversion Time Condition Sample & Hold (Cycles from Start of Conversion) First conversion 13.5 25 Normal conversions 1.5 13 2 13.5 2.5 14 Auto Triggered conversions Free Running conversion 16.6 Conversion Time (Cycles) Changing Channel or Reference Selection The MUX5:0 and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access.
ATtiny24/44/84 selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. 16.6.2 16.7 ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either VCC, or internal 1.1V reference, or external AREF pin.
Figure 16-8. Analog Input Circuitry IIH ADCn 1..100 kohm CS/H = 14 pF IIL VCC/2 Note: 16.9 The capacitor in the figure depicts the total capacitance, including the sample/hold capacitor and any stray or parasitic capacitance inside the device. The value given is worst case. Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements.
ATtiny24/44/84 • Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 16-9. Offset Error Output Code Ideal ADC Actual ADC Offset Error VREF Input Voltage • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 16-10.
• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 16-11. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 16-12.
ATtiny24/44/84 • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB. 16.
to perform a quick polarity check of the result, it is sufficient to read the MSB of the result (ADC9 in ADCH). If the bit is one, the result is negative, and if this bit is zero, the result is positive. As default the ADC converter operates in the unipolar input mode, but the bipolar input mode can be selected by writting the BIN bit in the ADCSRB to one.
ATtiny24/44/84 16.13 Register Description 16.13.1 ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 0x07 (0x27) REFS1 REFS0 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADMUX • Bit 7:6 – REFS1:REFS0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 16-3. Table 16-3.
done by first turning off the ADC, then changing multiplexer settings and then turn on the ADC. Alternatively, the first conversion results after changing multiplexer settings should be discarded. Table 16-4. Single-Ended Input channel Selections.
ATtiny24/44/84 Table 16-5. Differential Input channel Selections.
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. • Bit 5 – ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled.
ATtiny24/44/84 16.13.3 16.13.3.1 ADCL and ADCH – ADC Data Register ADLAR = 0 Bit 15 14 13 12 11 10 9 8 0x05 (0x25) – – – – – – ADC9 ADC8 ADCH 0x04 (0x24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 Read/Write Initial Value 16.13.3.
• Bit 6 – ACME: Analog Comparator Multiplexer Enable See “ADCSRB – ADC Control and Status Register B” on page 131. • Bit 5 – Res: Reserved Bit This is a reserved bit in ATtiny24/44/84. For compatibility with future devices always write this bit to zero. • Bit 4 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted.
ATtiny24/44/84 17. debugWIRE On-chip Debug System 17.1 Features • • • • • • • • • • 17.
When designing a system where debugWIRE will be used, the following must be observed: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. • Connecting the RESET pin directly to VCC will not work. • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 17.4 Software Break Points debugWIRE supports Program memory Break Points by the AVR Break instruction.
ATtiny24/44/84 18. Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The SPM instruction is disabled by default but it can be enabled by programming the SELFPRGEN fuse (to “0”). The Program memory is updated in a page by page fashion.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 18.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. Note: 18.4 The CPU is halted during the Page Write operation.
ATtiny24/44/84 18.5 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 18.
To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 Refer to Table 19-4 on page 160 for detailed description and mapping of the Fuse High Byte. To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and repeat the previous procedure.
ATtiny24/44/84 If successful, the contents of the destination register are as described in section “Device Signature Imprint Table” on page 161. 18.7 Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied.
• Bit 5 – RSIG: Read Device Signature Imprint Table Issuing an LPM instruction within three cycles after RSIG and SPMEN bits have been set in SPMCSR will return the selected data (depending on Z-pointer value) from the device signature imprint table into the destination register. See “Device Signature Imprint Table” on page 161 for details.
ATtiny24/44/84 19. Memory Programming This section describes the different methods for programming ATtiny24/44/84 memories. 19.1 Program And Data Memory Lock Bits The ATtiny24/44/84 provides two lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in Table 19-2. The lock bits can only be erased to “1” with the Chip Erase command. The device has no separate boot loader section.
19.2 Fuse Bytes The ATtiny24/44/84 have three fuse bytes. Table 19-3, Table 19-4 and Table 19-5 briefly describe the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed.. Table 19-3.
ATtiny24/44/84 Table 19-5.
19.3.1 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and High-voltage Programming mode, also when the device is locked. Signature bytes can also be read by the device firmware. See section “Reading Lock, Fuse and Signature Data from Software” on page 155. The three signature bytes reside in a separate address space called the device signature imprint table.
ATtiny24/44/84 19.5 Serial Programming Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). See Figure 19-1 below. Figure 19-1. Serial Programming and Verify +1.8 - 5.5V VCC MOSI MISO SCK RESET GND Note: If clocked by internal oscillator there is no need to connect a clock source to the CLKI pin.
instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: • Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz • High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz 19.5.
ATtiny24/44/84 next page (See Table 19-11 on page 165). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off. Table 19-11.
Table 19-12.
ATtiny24/44/84 If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the next instruction is carried out. Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 19-2 on page 166. 19.
19.7 High-Voltage Serial Programming Algorithm To program and verify the ATtiny24/44/84 in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in Table 19-16 on page 171): 19.7.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming mode: 1. Set Prog_enable pins listed in Table 19-14 on page 167 to “000”, RESET pin and VCC to 0V. 2. Apply 4.5 - 5.5V between VCC and GND.
ATtiny24/44/84 19.7.2 Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. • The command needs only be loaded once when writing or reading multiple memory locations. • Skip writing the data value 0xFF that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase.
Figure 19-4. Addressing the Flash which is Organized in Pages PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Figure 19-5. High-voltage Serial Programming Waveforms SDI PB0 MSB LSB SII PB1 MSB LSB SDO PB2 SCI PB3 19.7.5 MSB 0 LSB 1 2 3 4 5 6 7 8 9 10 Programming the EEPROM The EEPROM is organized in pages, see Table 20-12 on page 183.
ATtiny24/44/84 19.7.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to Table 19-16 on page 171): 1. Load Command "Read Flash". 2. Read Flash Low and High Bytes. The contents at the selected address are available at serial output SDO. 19.7.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to Table 19-16 on page 171): 1. Load Command “Read EEPROM”. 2. Read EEPROM Byte.
Table 19-16. High-voltage Serial Programming Instruction Set for ATtiny24/44/84 (Continued) Instruction Format Instruction Instr.1/5 Instr.2/6 Instr.3/7 Instr.
ATtiny24/44/84 Table 19-16. High-voltage Serial Programming Instruction Set for ATtiny24/44/84 (Continued) Instruction Format Instruction Write Lock Bits Read Fuse Low Bits Read Fuse High Bits Instr.1/5 Instr.2/6 Instr.3/7 Instr.
20. Electrical Characteristics 20.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
ATtiny24/44/84 Table 20-1. Symbol DC Characteristics. TA = -40°C to +85°C (Continued) Parameter Power Supply Current ICC Power-down mode Notes: Typ (1) Max (1) Units Active 1MHz, VCC = 2V 0.33 0.8 mA Active 4MHz, VCC = 3V 1.6 2.5 mA Active 8MHz, VCC = 5V 5 9 mA Idle 1MHz, VCC = 2V 0.11 0.4 mA Idle 4MHz, VCC = 3V 0.4 1.0 mA Idle 8MHz, VCC = 5V 1.5 3.5 mA WDT enabled, VCC = 3V 4.5 10 µA WDT disabled, VCC = 3V 0.15 2 µA Condition Min (1) 1.
Figure 20-2. Maximum Frequency vs. VCC (ATtiny24/44/84) 20 MHz 10 MHz Safe Operating Area 2.7V 20.4 20.4.1 4.5V 5.5V Clock Characteristics Accuracy of Calibrated Internal RC Oscillator It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics can be found in Figure 21-40 on page 206 and Figure 21-41 on page 206. Table 20-2.
ATtiny24/44/84 20.4.2 External Clock Drive Figure 20-3. External Clock Drive Waveform V IH1 V IL1 Table 20-3. External Clock Drive Characteristics VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Symbol Parameter 1/tCLCL Clock Frequency tCLCL Clock Period 250 100 50 ns tCHCX High Time 100 40 20 ns tCLCX Low Time 100 40 20 ns tCLCH Rise Time 2.0 1.6 0.5 μs tCHCL Fall Time 2.0 1.6 0.5 μs ΔtCLCL Change in period from one clock cycle to the next 2 2 2 % 20.
Two versions of power-on reset have been implemented, as follows. 20.5.1 Standard Power-On Reset This implementation of power-on reset existed in early versions of ATtiny24/44/84. The table below describes the characteristics of this power-on reset and it is valid for the following devices, only: • ATtiny24, revision D, and older • ATtiny44, revision C, and older • ATtiny84, revision A Note: Revisions are marked on the package (packages 14P3 and 14S1: bottom, package 20M1: top) Table 20-5.
ATtiny24/44/84 20.5.3 Brown-Out Detection Table 20-7. VBOT vs. BODLEVEL Fuse Coding BODLEVEL [2..0] Fuses Min(1) 111 20.6 Max(1) 110 1.7 1.8 2.0 101 2.5 2.7 2.9 100 4.1 4.3 4.5 Reserved 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test.
20.7 ADC Characteristics – Preliminary Data Table 20-9. Symbol ADC Characteristics, Single Ended Channels. T = -40°C - 85°C Parameter Condition Min(1) Typ(1) Resolution Units 10 Bits VREF = 4V, VCC = 4V, ADC clock = 200 kHz 2.0 TBD LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz 2.5 TBD LSB VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 1.5 TBD LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 2.
ATtiny24/44/84 Table 20-10. ADC Characteristics, Differential Channels (Unipolar Mode), TA = -40°C to 85°C Symbol Parameter Max(1) Units Gain = 1x 10 Bits Gain = 20x 10 Bits Condition Min(1) Typ(1) Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 10.0 TBD LSB Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 20.
Table 20-11. ADC Characteristics, Differential Channels (Bipolar Mode), TA = -40°C to 85°C Symbol Parameter Max(1) Units Gain = 1x 10 Bits Gain = 20x 10 Bits Condition Min(1) Typ(1) Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 8.0 TBD LSB Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 8.
ATtiny24/44/84 20.8 Serial Programming Characteristics Figure 20-4. Serial Programming Timing MOSI SCK tSLSH tSHOX tOVSH tSHSL MISO Figure 20-5. Serial Programming Waveform SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Table 20-12. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 1.8 - 5.
20.9 High-Voltage Serial Programming Characteristics Figure 20-6. High-voltage Serial Programming Timing SDI (PA6), SII (PA5) tIVSH SCI (PB0) tSLSH tSHIX tSHSL SDO (PA4) tSHOV Table 20-13.
ATtiny24/44/84 21. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing.
Table 21-2. Additional Current Consumption (percentage) in Active and Idle mode Current consumption additional to active mode with external clock (see Figure 21-1 and Figure 21-2) PRR bit 21.1.1 Current consumption additional to idle mode with external clock (see Figure 21-6 and Figure 21-7) PRTIM1 1.8 % 8.0 % PRTIM0 2.3 % 10.4 % PRUSI 1.4 % 6.1 % PRADC 6.7 % 28.8 % Example Calculate the expected current consumption in idle mode with USI, TIMER0, and ADC enabled at VCC = 2.0V and f = 1MHz.
ATtiny24/44/84 Figure 21-2. Active Supply Current vs. frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY (PRR=0xFF) 14 5.5 V 12 5.0 V ICC (mA) 10 4.5 V 8 6 4.0 V 4 3.3 V 2.7 V 2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 21-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL RC OSCILLATOR, 8 MHz 6 25 °C 5 -40 °C 85 °C ICC (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 21-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 1.2 85 °C 25 °C -40 °C 1 ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 21-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 128 KHz 0.14 -40 °C 25 °C 85 °C 0.12 ICC (mA) 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny24/44/84 21.3 Idle Supply Current Figure 21-6. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY (PRR=0xFF) ICC (mA) 0.18 0.16 5.5 V 0.14 5.0 V 0.12 4.5 V 0.1 4.0 V 0.08 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 21-7. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY (PRR=0xFF) 5 4.5 4 ICC (mA) 3.5 5.5 V 3 5.0 V 2.5 4.5 V 2 1.5 4.0 V 3.
Figure 21-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 2 1.8 1.6 85 °C 1.4 25 °C -40 °C ICC (mA) 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 21-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 0.35 85 °C 0.3 25 °C -40 °C ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny24/44/84 Figure 21-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 128 KHz 0.03 -40 °C 25 °C 0.025 85 °C ICC (mA) 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 21.4 Power-down Supply Current Figure 21-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 0.7 85 °C 0.6 ICC (uA) 0.5 0.4 0.3 0.2 25 °C 0.1 -40 °C 0 1.5 2 2.
Figure 21-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 10 9 -40 °C 8 25 °C 85 °C 7 ICC (uA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 21.5 Standby Supply Current Figure 21-13. Standby Supply Current vs. VCC (4 MHz External Crystal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 4 MHz EXTERNAL CRYSTAL, WATCHDOG TIMER DISABLED I CC (mA) 0.14 0.12 85 ˚C 0.1 25 ˚C 0.08 -40 ˚C 0.06 0.04 0.
ATtiny24/44/84 21.6 Pin Pull-up Figure 21-14. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 1.8V 50 45 40 IOP (uA) 35 30 25 20 15 10 25 ˚C 5 85 ˚C -40 ˚C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) Figure 21-15. I/O Pin Pull-up Resistor Current vs. input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 80 70 60 IOP (uA) 50 40 30 20 25 ˚C 10 85 ˚C -40 ˚C 0 0 0.5 1 1.
Figure 21-16. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 5V 160 140 120 IOP (uA) 100 80 60 40 25 ˚C 20 85 ˚C -40 ˚C 0 0 1 2 3 4 5 6 VOP (V) Figure 21-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 1.8V 40 35 I RESET (uA) 30 25 20 15 10 25 ˚C 5 -40 ˚C 85 ˚C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATtiny24/44/84 Figure 21-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 2.7V 60 50 I RESET(uA) 40 30 20 25 ˚C 10 -40 ˚C 85 ˚C 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 21-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs.
21.7 Pin Driver Strength Figure 21-20. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 1 0.9 85 ˚C 0.8 VOL (V) 0.7 25 ˚C 0.6 -40 ˚C 0.5 0.4 0.3 0.2 0.1 0 0 5 10 15 20 25 IOL (mA) Figure 21-21. I/O pin Output Voltage vs. Sink Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 0.7 0.6 85 ˚C VOL (V) 0.5 25 ˚C 0.4 -40 ˚C 0.3 0.2 0.
ATtiny24/44/84 Figure 21-22. I/O Pin Output Voltage vs. Source Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V 3.5 3 VOH (V) 2.5 -40 ˚C 25 ˚C 85 ˚C 2 1.5 1 0.5 0 0 5 10 15 20 25 IOH (mA) Figure 21-23. I/O Pin output Voltage vs. Source Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5.1 5 4.9 VOH (V) 4.8 4.7 4.6 -40 ˚C 4.5 25 ˚C 85 ˚C 4.4 4.
Figure 21-24. Reset Pin Output Voltage vs. Sink Current (VCC = 3V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 1.5 85 °C VOL (V) 1 0 °C -45 °C 0.5 0 0 0.5 1 1.5 2 2.5 3 IOL (mA) Figure 21-25. Reset Pin Output Voltage vs. Sink Current (VCC = 5V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 1 0.8 VOL (V) 0.6 85 °C 0.4 0 °C -45 °C 0.2 0 0 0.5 1 1.5 2 2.
ATtiny24/44/84 Figure 21-26. Reset Pin Output Voltage vs. Source Current (VCC = 3V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V 3.5 3 VOH (V) 2.5 2 1.5 -45 °C 25 °C 85 °C 1 0.5 0 0 0.5 1 1.5 2 IOH (mA) Figure 21-27. Reset Pin Output Voltage vs. Source Current (VCC = 5V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5 4.5 VOH (V) 4 3.5 3 -45 °C 25 °C 85 °C 2.5 0 0.5 1 1.
21.8 Pin Threshold and Hysteresis Figure 21-28. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 3.5 85 ˚C 25 ˚C -40 ˚C Threshold (V) 3 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 21-29. I/O Pin Input threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 2.5 85 ˚C 25 ˚C Threshold (V) 2 -40 ˚C 1.5 1 0.5 0 1.5 2 2.5 3 3.
ATtiny24/44/84 Figure 21-30. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 0.6 Input Hysteresis (V) 0.5 85 °C -40 °C 0.4 25 °C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 21-31. Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin Threshold as ‘1’) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2.5 -40 ˚C 25 ˚C 2 Threshold (V) 85 ˚C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 21-32. Reset Input Threshold Voltage vs. VCC (VIL, I/O pin Read as ‘0’) RESET INPUT THRESHOLD VOLTAGE vs. V CC VIL, IO PIN READ AS '0' 2.5 85 ˚C 25 ˚C 2 Threshold (V) -40 ˚C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 21-33. Reset Pin Input Hysteresis vs. VCC RESET PIN INPUT HYSTERESIS vs. VCC 0.8 Input Hysteresis (V) 0.7 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny24/44/84 Figure 21-34. Reset Pin Input Hysteresis vs. VCC (Reset Pin Used as I/O) RESET PIN AS I/O, INPUT HYSTERESIS vs. VCC VIL, I/O PIN READ AS "0" 1 0.9 0.8 Input Hysteresis (mV) -40 °C 0.7 25 °C 0.6 85 °C 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 21.9 BOD Threshold and Analog Comparator Offset Figure 21-35. BOD Threshold vs. Temperature (BODLEVEL is 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL is 4.3V 4.34 4.32 Rising Vcc Threshold (V) 4.3 4.28 4.26 4.24 4.
Figure 21-36. BOD Threshold vs, Temperature (BODLEVEL is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL is 2.7V 2.75 Rising Vcc 2.74 2.73 Threshold (V) 2.72 2.71 2.7 2.69 2.68 2.67 Falling Vcc 2.66 2.65 2.64 -60 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 21-37. BOD Threshold vs. Temperature (BODLEVEL is 1.8V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL is 1.8V 1.82 Rising Vcc 1.815 Threshold (V) 1.81 1.805 1.8 1.795 1.79 Falling Vcc 1.785 1.78 1.775 1.
ATtiny24/44/84 21.10 Internal Oscillator Speed Figure 21-38. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 110 109 108 Frequency (kHz) 107 -40 °C 106 105 25 °C 104 103 102 101 85 °C 100 99 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 21-39. Watchdog Oscillator Frequency vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 110 109 108 Frequency (kHz) 107 106 105 104 1.8 V 103 2.7 V 102 3.3 V 101 4.0 V 5.
Figure 21-40. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 9 85 °C 8 25 °C -40 °C Frequency (MHz) 7 6 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 21-41. Calibrated 8 MHz RC oscillator Frequency vs. Temperature CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.3 5.0 V 8.2 3.0 V Frequency (MHz) 8.1 8 7.9 7.8 7.7 7.
ATtiny24/44/84 Figure 21-42. Calibrated 8 MHz RC Oscillator Frequency vs, OSCCAL Value CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 16 FRC (MHz) 85 ˚C 14 25 ˚C 12 -40 ˚C 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) 21.11 Current Consumption of Peripheral Units Figure 21-43. ADC Current vs. VCC ADC CURRENT vs. VCC 4.0 MHz FREQUENCY 700 600 ICC (uA) 500 400 300 200 100 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 21-44. AREF External Reference Current vs. VCC AREF EXTERNAL REFERENCE CURRENT vs. VCC 180 25 ˚C 150 ICC (uA) 120 90 60 30 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 21-45. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs.
ATtiny24/44/84 Figure 21-46. Programming Current vs. VCC (ATtiny24) PROGRAMMING CURRENT vs. VCC ATtiny24 8000 7000 25 °C 6000 ICC (uA) 5000 4000 3000 2000 1000 0 1.5 2.5 3.5 4.5 5.5 VCC (V) Figure 21-47. Programming Current vs. VCC (ATtiny44) PROGRAMMING CURRENT vs. VCC ATtiny44 9000 8000 25 °C 7000 ICC (uA) 6000 5000 4000 3000 2000 1000 0 1.5 2.5 3.5 4.5 5.
Figure 21-48. Programming Current vs. VCC (ATtiny84) PROGRAMMING CURRENT vs. VCC ATtiny84 16000 25 °C 14000 12000 ICC (uA) 10000 8000 6000 4000 2000 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 21-49. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 45 40 35 ICC (uA) 30 85 ˚C 25 ˚C -40 ˚C 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny24/44/84 Figure 21-50. Watchdog Timer Current vs. VCC WATCHDOG TIMER CURRENT vs. VCC 10 9 -40 ˚C 85 ˚C 8 ICC (uA) 7 25 ˚C 6 5 4 3 2 1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 21.12 Current Consumption in Reset and Reset Pulsewidth Figure 21-51. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, excluding Current Through the Reset Pull-up) RESET SUPPLY CURRENT vs. VCC 0.1 - 1.0 MHz,EXCLUDING CURRENT THROUGH THE RESET PULLUP 0.14 5.5 V 0.12 5.0 V ICC (mA) 0.1 4.5 V 0.08 4.0 V 0.06 3.
Figure 21-52. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through the Reset Pull-up) RESET SUPPLY CURRENT vs. VCC 1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 3 2.5 5.5 V 5.0 V 4.5 V ICC (mA) 2 1.5 1 4.0V 3.3V 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 21-53. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs. VCC 2500 Pulsewidth (ns) 2000 1500 1000 500 85 ˚C 25 ˚C -40 ˚C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny24/44/84 22.
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them.
ATtiny24/44/84 23.
Mnemonics Operands Description Operation Flags #Clocks ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..
ATtiny24/44/84 24. Ordering Information 24.1 ATtiny24 Speed (MHz) 10 20 Notes: Power Supply Ordering Code(1) Package(2) 1.8 - 5.5V ATtiny24V-10SSU ATtiny24V-10PU ATtiny24V-10MU 14S1 14P3 20M1 Industrial (-40°C to 85°C) 2.7 - 5.5V ATtiny24-20SSU ATtiny24-20PU ATtiny24-20MU 14S1 14P3 20M1 Industrial (-40°C to 85°C) Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
24.2 ATtiny44 Speed (MHz) Power Supply Ordering Code(1) Package(2) 10 1.8 - 5.5V ATtiny44V-10SSU ATtiny44V-10PU ATtiny44V-10MU 14S1 14P3 20M1 Industrial (-40°C to 85°C) 20 2.7 - 5.5V ATtiny44-20SSU ATtiny44-20PU ATtiny44-20MU 14S1 14P3 20M1 Industrial (-40°C to 85°C) Notes: Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATtiny24/44/84 24.3 ATtiny84 Speed (MHz) Power Supply Ordering Code(1) Package(2) 10 1.8 - 5.5V ATtiny84V-10SSU ATtiny84V-10PU ATtiny84V-10MU 14S1 14P3 20M1 Industrial (-40°C to 85°C) 20 2.7 - 5.5V ATtiny84-20SSU ATtiny84-20PU ATtiny84-20MU 14S1 14P3 20M1 Industrial (-40°C to 85°C) Notes: Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
25. Packaging Information 25.1 20M1 D 1 Pin 1 ID 2 SIDE VIEW E 3 TOP VIEW A2 D2 A1 A 0.08 1 2 Pin #1 Notch (0.20 R) 3 COMMON DIMENSIONS (Unit of Measure = mm) E2 b L e BOTTOM VIEW SYMBOL MIN A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 b D D2 E2 L MAX NOTE 0.23 0.30 4.00 BSC 2.45 2.60 2.75 4.00 BSC 2.45 e Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. NOM 0.20 REF 0.18 E Note: C 2.60 2.75 0.50 BSC 0.35 0.40 0.
ATtiny24/44/84 25.2 14P3 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. This package conforms to JEDEC reference MS-001, Variation AA. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). MIN NOM MAX A – – 5.334 A1 0.381 – – D 18.669 – 19.685 E 7.620 – 8.255 E1 6.096 – 7.112 B 0.356 – 0.559 B1 1.143 – 1.778 L 2.921 – 3.810 C 0.
25.3 14S1 1 E H E N L Top View End View e COMMON DIMENSIONS (Unit of Measure = mm/inches) b SYMBOL A1 A D Side View NOM MAX – 1.75/0.0688 NOTE 1.35/0.0532 A1 0.1/.0040 – 0.25/0.0098 b 0.33/0.0130 – 0.5/0.0200 5 D 8.55/0.3367 – 8.74/0.3444 2 E 3.8/0.1497 – 3.99/0.1574 3 H 5.8/0.2284 – 6.19/0.2440 L 0.41/0.0160 – 1.27/0.0500 e Notes: MIN A 4 1.27/0.050 BSC 1.
ATtiny24/44/84 26. Errata The revision letters in this section refer to the revision of the corresponding ATtiny24/44/84 device. 26.1 26.1.1 ATtiny24 Rev. D – E No known errata. 26.1.2 Rev. C • Reading EEPROM when system clock frequency is below 900 kHz may not work 1. Reading EEPROM when system clock frequency is below 900 kHz may not work Reading data from the EEPROM at system clock frequency below 900 kHz may result in wrong data read.
26.2 26.2.1 ATtiny44 Rev. B – D No known errata. 26.2.2 Rev. A • Reading EEPROM when system clock frequency is below 900 kHz may not work 1. Reading EEPROM when system clock frequency is below 900 kHz may not work Reading data from the EEPROM at system clock frequency below 900 kHz may result in wrong data read. Problem Fix/Work around Avoid using the EEPROM at clock frequency below 900 kHz.
ATtiny24/44/84 26.3 26.3.1 ATtiny84 Rev. A – B No known errata.
27. Datasheet Revision History 27.1 Rev H. 10/09 1. Updated document template. Re-arranged some sections. 2. Updated “Low-Frequency Crystal Oscillator” with the Table 6-8 on page 28 3. Updated Tables: – “Active Clock Domains and Wake-up Sources in Different Sleep Modes” on page 33 – “DC Characteristics” on page 174 – “Register Summary” on page 213 4. Updated Register Description: – “ADMUX – ADC Multiplexer Selection Register” on page 145 5.
ATtiny24/44/84 – “Prescaling and Conversion Timing” on page 135 – “Temperature Measurement” on page 144 – “ADMUX – ADC Multiplexer Selection Register” on page 145 – “Limitations of debugWIRE” on page 152 – “Reading Lock, Fuse and Signature Data from Software” on page 155 – “Device Signature Imprint Table” on page 161 – “Enter High-voltage Serial Programming Mode” on page 168 – “Absolute Maximum Ratings*” on page 174 – “DC Characteristics” on page 174 – “Speed Grades” on page 175 – “Clock Characteristics” on
– “Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)” on page 190 – “Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)” on page 190 – “Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)” on page 191 – “Power-down Supply Current vs. VCC (Watchdog Timer Disabled)” on page 191 – “Power-down Supply Current vs. VCC (Watchdog Timer Enabled)” on page 192 – “Reset Pin Input Hysteresis vs. VCC” on page 202 – “Reset Pin Input Hysteresis vs.
ATtiny24/44/84 – “VBOT vs. BODLEVEL Fuse Coding” on page 179 – “ADC Characteristics, Single Ended Channels. T = -40°C - 85°C” on page 180 – “ADC Characteristics, Differential Channels (Bipolar Mode), TA = -40°C to 85°C” on page 182 – “Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 1.8 - 5.5V (Unless Otherwise Noted)” on page 183 – “High-voltage Serial Programming Characteristics TA = 25°C, VCC = 5V (Unless otherwise noted)” on page 184 6.
27.5 27.6 27.7 Rev D. 08/06 1. 2. 3. 4. 5. 6. Updated “Calibrated Internal 8 MHz Oscillator” on page 26. Updated “OSCCAL – Oscillator Calibration Register” on page 30. Added Table 20-2 on page 176. Updated code examples in “SPI Master Operation Example” on page 119. Updated code examples in “SPI Slave Operation Example” on page 121. Updated “Signature Bytes” on page 162. 1. 2. 3. 4. Updated Features in “USI – Universal Serial Interface” on page 117. Added “Clock speed considerations” on page 123.
ATtiny24/44/84 Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1 Pin Descriptions .................................................................................................2 2 Overview ................................................................................................... 4 3 About ............
8 9 7.3 Power Reduction Register ...............................................................................35 7.4 Minimizing Power Consumption ......................................................................35 7.5 Register Description ........................................................................................36 System Control and Reset .................................................................... 39 8.1 Resetting the AVR ...............................................
ATtiny24/44/84 12.7 Compare Match Output Unit ............................................................................94 12.8 Modes of Operation .........................................................................................96 12.9 Timer/Counter Timing Diagrams ...................................................................103 12.10 Accessing 16-bit Registers ............................................................................105 12.11 Register Description ................
17.2 Overview ........................................................................................................151 17.3 Physical Interface ..........................................................................................151 17.4 Software Break Points ...................................................................................152 17.5 Limitations of debugWIRE .............................................................................152 17.6 Register Description ............
ATtiny24/44/84 21.2 Active Supply Current ....................................................................................186 21.3 Idle Supply Current ........................................................................................189 21.4 Power-down Supply Current ..........................................................................191 21.5 Standby Supply Current ................................................................................192 21.6 Pin Pull-up ..................
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