Datasheet

4
ATtiny40 [SUMMARY DATASHEET]
8263BS–AVR–01/2013
accessed in one single instruction executed in one clock cycle. The resulting architecture is compact and code effi-
cient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATtiny40 provides the following features: 4K bytes of In-System Programmable Flash, 256 bytes of SRAM,
twelve general purpose I/O lines, 16 general purpose working registers, an 8-bit Timer/Counter with two PWM
channels, a 8/16-bit Timer/Counter, Internal and External Interrupts, an eight-channel, 10-bit ADC, a programma-
ble Watchdog Timer with internal oscillator, a slave two-wire interface, a master/slave serial peripheral interface,
an internal calibrated oscillator, and four software selectable power saving modes.
Idle mode stops the CPU while allowing the Timer/Counter, ADC, Analog Comparator, SPI, TWI, and interrupt sys-
tem to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by
stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all
chip functions are disabled until the next interrupt or hardware reset. In Standby mode, the oscillator is running
while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption.
STACK
POINTER
SRAM
PROGRAM
COUNTER
PROGRAMMING
LOGIC
ISP
INTERFACE
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
RESET FLAG
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER0
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
INTERRUPT
UNIT
ANALOG
COMPARATOR
ADC
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
V
CC
RESET
DATA REGISTER
PORT A
DIRECTION
REG. PORT A
DRIVERS
PORT A
GND
PA[7:0]
8-BIT DATA BUS
TIMER/
COUNTER1
TWI
SPI
DATA REGISTER
PORT B
DIRECTION
REG. PORT B
DRIVERS
PORT B
PB[3:0]
DATA REGISTER
PORT C
DIRECTION
REG. PORT C
DRIVERS
PORT C
PC[5:0]