Datasheet
2
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
1. Pin Configurations
Figure 1-1. Pinout ATtiny25/45/85
1.1 Pin Descriptions
1.1.1 VCC
Supply voltage.
1.1.2 GND
Ground.
1.1.3 Port B (PB5:PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
1
2
3
4
8
7
6
5
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
GND
VCC
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
PDIP/SOIC/TSSOP
1
2
3
4
5
QFN/MLF
15
14
13
12
11
20
19
18
17
16
6
7
8
9
10
DNC
DNC
GND
DNC
DNC
DNC
DNC
DNC
DNC
DNC
NOTE: Bottom pad should be soldered to ground.
DNC: Do Not Connect
NOTE: TSSOP only for ATtiny45/V
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
DNC
DNC
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
VCC
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
DNC
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)