Datasheet

4
8183FS–AVR–06/12
ATtiny24A/44A/84A
2. Overview
ATtiny24A/44A/84A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny24A/44A/84A achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
WATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMER/
COUNTER0
DATA DIR.
REG.PORT A
DATA REGISTER
PORT A
PROGRAMMING
LOGIC
TIMING AND
CONTROL
MCU STATUS
REGISTER
PORT A DRIVERS
PA[7:0]
VCC
GND
+
_
ANALOG
COMPARATOR
8-BIT DATABUS
ADC
ISP INTERFACE
INTERRUPT
UNIT
EEPROM
INTERNAL
OSCILLATOR
OSCILLATORS
CALIBRATED
OSCILLATOR
INTERNAL
DATA DIR.
REG.PORT B
DATA REGISTER
PORT B
PORT B DRIVERS
PB[3:0]
PROGRAM
COUNTER
STACK
POINTER
PROGRAM
FLASH
SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
STATUS
REGISTER
Z
Y
X
ALU
CONTROL
LINES
TIMER/
COUNTER1