Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFN 20 (4x4) 8-Bit 20 MHz I/O number 12

Table Of Contents

Features
1. Pin Configurations
- 1.1 Pin Descriptions
2. Overview
3. About
- 3.1 Resources
- 3.2 Code Examples
- 3.3 Data Retention
- 3.4 Disclaimer
4. CPU Core
- 4.1 Architectural Overview
- 4.2 ALU – Arithmetic Logic Unit
- 4.3 Status Register
  - 4.3.1 SREG – AVR Status Register
- 4.4 General Purpose Register File
  - 4.4.1 The X-register, Y-register, and Z-register
- 4.5 Stack Pointer
  - 4.5.1 SPH and SPL — Stack Pointer Register
- 4.6 Instruction Execution Timing
- 4.7 Reset and Interrupt Handling
  - 4.7.1 Interrupt Response Time
5. Memories
- 5.1 In-System Re-programmable Flash Program Memory
- 5.2 SRAM Data Memory
  - 5.2.1 Data Memory Access Times
- 5.3 EEPROM Data Memory
- 5.4 I/O Memory
  - 5.4.1 General Purpose I/O Registers
- 5.5 Register Description
6. Clock System
- 6.1 Clock Subsystems
- 6.2 Clock Sources
- 6.3 System Clock Prescaler
  - 6.3.1 Switching Time
- 6.4 Clock Output Buffer
- 6.5 Register Description
  - 6.5.1 OSCCAL – Oscillator Calibration Register
  - 6.5.2 CLKPR – Clock Prescale Register
7. Power Management and Sleep Modes
- 7.1 Sleep Modes
- 7.2 Software BOD Disable
  - 7.2.1 Limitations
- 7.3 Power Reduction Register
- 7.4 Minimizing Power Consumption
- 7.5 Register Description
  - 7.5.1 MCUCR – MCU Control Register
  - 7.5.2 PRR – Power Reduction Register
8. System Control and Reset
- 8.1 Resetting the AVR
- 8.2 Reset Sources
- 8.3 Internal Voltage Reference
  - 8.3.1 Voltage Reference Enable Signals and Start-up Time
- 8.4 Watchdog Timer
  - 8.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer
    - 8.4.1.1 Safety Level 1
    - 8.4.1.2 Safety Level 2
  - 8.4.2 Code Example
- 8.5 Register Description
  - 8.5.1 MCUSR – MCU Status Register
  - 8.5.2 WDTCSR – Watchdog Timer Control and Status Register
9. Interrupts
- 9.1 Interrupt Vectors
- 9.2 External Interrupts
  - 9.2.1 Low Level Interrupt
  - 9.2.2 Pin Change Interrupt Timing
- 9.3 Register Description
10. I/O Ports
- 10.1 Ports as General Digital I/O
- 10.2 Alternate Port Functions
  - 10.2.1 Alternate Functions of Port A
  - 10.2.2 Alternate Functions of Port B
- 10.3 Register Description
11. 8-bit Timer/Counter0 with PWM
- 11.1 Features
- 11.2 Overview
  - 11.2.1 Registers
  - 11.2.2 Definitions
- 11.3 Clock Sources
- 11.4 Counter Unit
- 11.5 Output Compare Unit
- 11.6 Compare Match Output Unit
  - 11.6.1 Compare Output Mode and Waveform Generation
- 11.7 Modes of Operation
- 11.8 Timer/Counter Timing Diagrams
- 11.9 Register Description
12. 16-bit Timer/Counter1
- 12.1 Features
- 12.2 Overview
- 12.3 Timer/Counter Clock Sources
- 12.4 Counter Unit
- 12.5 Input Capture Unit
- 12.6 Output Compare Units
- 12.7 Compare Match Output Unit
  - 12.7.1 Compare Output Mode and Waveform Generation
- 12.8 Modes of Operation
- 12.9 Timer/Counter Timing Diagrams
- 12.10 Accessing 16-bit Registers
  - 12.10.1 Reusing the Temporary High Byte Register
- 12.11 Register Description
13. Timer/Counter Prescaler
- 13.1 Prescaler Reset
- 13.2 External Clock Source
- 13.3 Register Description
  - 13.3.1 GTCCR – General Timer/Counter Control Register
14. USI – Universal Serial Interface
- 14.1 Features
- 14.2 Overview
- 14.3 Functional Descriptions
- 14.4 Alternative USI Usage
- 14.5 Register Descriptions
15. Analog Comparator
- 15.1 Analog Comparator Multiplexed Input
- 15.2 Register Description
16. Analog to Digital Converter
- 16.1 Features
- 16.2 Overview
- 16.3 Operation
- 16.4 Starting a Conversion
- 16.5 Prescaling and Conversion Timing
- 16.6 Changing Channel or Reference Selection
  - 16.6.1 ADC Input Channels
  - 16.6.2 ADC Voltage Reference
- 16.7 ADC Noise Canceler
- 16.8 Analog Input Circuitry
- 16.9 Noise Canceling Techniques
- 16.10 ADC Accuracy Definitions
- 16.11 ADC Conversion Result
- 16.12 Temperature Measurement
- 16.13 Register Description
17. debugWIRE On-chip Debug System
- 17.1 Features
- 17.2 Overview
- 17.3 Physical Interface
- 17.4 Software Break Points
- 17.5 Limitations of debugWIRE
- 17.6 Register Description
  - 17.6.1 DWDR – debugWire Data Register
18. Self-Programming the Flash
- 18.1 Performing Page Erase by SPM
- 18.2 Filling the Temporary Buffer (Page Loading)
- 18.3 Performing a Page Write
- 18.4 Addressing the Flash During Self-Programming
- 18.5 EEPROM Write Prevents Writing to SPMCSR
- 18.6 Reading Lock, Fuse and Signature Data from Software
- 18.7 Preventing Flash Corruption
- 18.8 Programming Time for Flash when Using SPM
- 18.9 Register Description
  - 18.9.1 SPMCSR – Store Program Memory Control and Status Register
19. Memory Programming
- 19.1 Program And Data Memory Lock Bits
- 19.2 Fuse Bytes
  - 19.2.1 Latching of Fuses
- 19.3 Device Signature Imprint Table
  - 19.3.1 Signature Bytes
  - 19.3.2 Calibration Byte
- 19.4 Page Size
- 19.5 Serial Programming
  - 19.5.1 Serial Programming Algorithm
  - 19.5.2 Serial Programming Instruction set
- 19.6 High-voltage Serial Programming
- 19.7 High-Voltage Serial Programming Algorithm
20. Electrical Characteristics
- 20.1 Absolute Maximum Ratings*
- 20.2 DC Characteristics
- 20.3 Speed
- 20.4 Clock Characteristics
  - 20.4.1 Accuracy of Calibrated Internal RC Oscillator
  - 20.4.2 External Clock Drive
- 20.5 System and Reset Characteristics
- 20.6 Analog Comparator Characteristics
- 20.7 ADC Characteristics
- 20.8 Serial Programming Characteristics
- 20.9 High-Voltage Serial Programming Characteristics
21. Typical Characteristics
- 21.1 Supply Current of I/O Modules
  - 21.1.1 Example
- 21.2 Active Supply Current
- 21.3 Idle Supply Current
- 21.4 Power-down Supply Current
- 21.5 Standby Supply Current
- 21.6 Pin Pull-up
- 21.7 Pin Driver Strength
- 21.8 Pin Threshold and Hysteresis
- 21.9 BOD Threshold and Analog Comparator Offset
- 21.10 Internal Oscillator Speed
- 21.11 Current Consumption of Peripheral Units
- 21.12 Current Consumption in Reset and Reset Pulsewidth
22. Register Summary
23. Instruction Set Summary
24. Ordering Information
- 24.1 ATtiny24
- 24.2 ATtiny44
- 24.3 ATtiny84
25. Packaging Information
- 25.1 20M1
- 25.2 14P3
- 25.3 14S1
26. Errata
- 26.1 ATtiny24
- 26.2 ATtiny44
  - 26.2.1 Rev. B – D
  - 26.2.2 Rev. A
- 26.3 ATtiny84
  - 26.3.1 Rev. A – B
27. Datasheet Revision History
- 27.1 Rev K. - 10/10
- 27.2 Rev J. - 08/10
- 27.3 Rev I. - 06/10
- 27.4 Rev H. 10/09
- 27.5 Rev G. 01/08
- 27.6 Rev F. 02/07
- 27.7 Rev E. 09/06
- 27.8 Rev D. 08/06
- 27.9 Rev C. 07/06
- 27.10 Rev B. 05/06
- 27.11 Rev A. 12/05
Table of Contents

8006K–AVR–10/10

ATtiny24/44/84

Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Fig-

ure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally

in the modules having the alternate function.

The following subsections shortly describe the alternate functions for each port, and relate the

overriding signals to the alternate function. Refer to the alternate function description for further

details.

Table 10-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name Description

PUOE

Pull-up Override

Enable

If this signal is set, the pull-up enable is controlled by the PUOV

signal. If this signal is cleared, the pull-up is enabled when

{DDxn, PORTxn, PUD} = 0b010.

PUOV

Pull-up Override

Value

If PUOE is set, the pull-up is enabled/disabled when PUOV is

set/cleared, regardless of the setting of the DDxn, PORTxn,

and PUD Register bits.

DDOE

Data Direction

Override Enable

If this signal is set, the Output Driver Enable is controlled by the

DDOV signal. If this signal is cleared, the Output driver is

enabled by the DDxn Register bit.

DDOV

Data Direction

Override Value

If DDOE is set, the Output Driver is enabled/disabled when

DDOV is set/cleared, regardless of the setting of the DDxn

PVOE

Port Value

Override Enable

If this signal is set and the Output Driver is enabled, the port

value is controlled by the PVOV signal. If PVOE is cleared, and

the Output Driver is enabled, the port Value is controlled by the

PORTxn Register bit.

PVOV

Port Value

Override Value

If PVOE is set, the port value is set to PVOV, regardless of the

setting of the PORTxn Register bit.

PTOE

Port Toggle

Override Enable

If PTOE is set, the PORTxn Register bit is inverted.

DIEOE

Digital Input

Enable Override

Enable

If this bit is set, the Digital Input Enable is controlled by the

DIEOV signal. If this signal is cleared, the Digital Input Enable

is determined by MCU state (Normal mode, sleep mode).

DIEOV

Digital Input

Enable Override

Value

If DIEOE is set, the Digital Input is enabled/disabled when

DIEOV is set/cleared, regardless of the MCU state (Normal

mode, sleep mode).

DI Digital Input

This is the Digital Input to alternate functions. In the figure, the

signal is connected to the output of the schmitt-trigger but

before the synchronizer. Unless the Digital Input is used as a

clock source, the module with the alternate function will use its

own synchronizer.

AIO

Analog

Input/Output

This is the Analog Input/Output to/from alternate functions. The

signal is connected directly to the pad, and can be used bi-

directionally.