Datasheet

30
8006K–AVR–10/10
ATtiny24/44/84
6.2.6 Default Clock Source
The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default
clock source setting is therefore the Internal Oscillator running at 8.0 MHz with longest start-up
time and an initial system clock prescaling of 8, resulting in 1.0 MHz system clock. This default
setting ensures that all users can make their desired clock source setting using an in-system or
high-voltage programmer.
For low-voltage devices (ATtiny24V/44V/84V) it should be noted that unprogramming the
CKDIV8 fuse may result in overclocking. At low voltages (below 2.7V) the devices are rated for
maximum 4 MHz operation (see Section 20.3 on page 175), but routing the clock signal from the
internal oscillator directly to the system clock line will run the device at 8 MHz.
6.3 System Clock Prescaler
The ATtiny24/44/84 system clock can be divided by setting the “CLKPR – Clock Prescale Regis-
ter” on page 31. This feature can be used to decrease power consumption when the
requirement for processing power is low. This can be used with all clock source options, and it
will affect the clock frequency of the CPU and all synchronous peripherals. clk
I/O
, clk
ADC
, clk
CPU
,
and clk
FLASH
are divided by a factor as shown in Table 6-11 on page 32.
6.3.1 Switching Time
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither the
clock frequency corresponding to the previous setting, nor the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the
new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the
previous clock period, and T2 is the period corresponding to the new prescaler setting.
6.4 Clock Output Buffer
The device can output the system clock on the CKOUT pin. To enable the output, the CKOUT
fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. Note that the clock will not be output during reset and that the normal
operation of the I/O pin will be overridden when the fuse is programmed. Any clock source,
including the internal RC Oscillator, can be selected when the clock is output on CKOUT. If the
System Clock Prescaler is used, it is the divided system clock that is output.
6.5 Register Description
6.5.1 OSCCAL – Oscillator Calibration Register
• Bits 7:0 – CAL7:0: Oscillator Calibration Value
Bit 76543210
0x31 (0x51) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Device Specific Calibration Value