Datasheet
Table Of Contents
- Features
- 1. Pin Configurations
- 2. Overview
- 3. About
- 4. CPU Core
- 5. Memories
- 6. Clock System
- 7. Power Management and Sleep Modes
- 8. System Control and Reset
- 9. Interrupts
- 10. I/O Ports
- 11. 8-bit Timer/Counter0 with PWM
- 11.1 Features
- 11.2 Overview
- 11.3 Clock Sources
- 11.4 Counter Unit
- 11.5 Output Compare Unit
- 11.6 Compare Match Output Unit
- 11.7 Modes of Operation
- 11.8 Timer/Counter Timing Diagrams
- 11.9 Register Description
- 11.9.1 TCCR0A – Timer/Counter Control Register A
- 11.9.2 TCCR0B – Timer/Counter Control Register B
- 11.9.3 TCNT0 – Timer/Counter Register
- 11.9.4 OCR0A – Output Compare Register A
- 11.9.5 OCR0B – Output Compare Register B
- 11.9.6 TIMSK0 – Timer/Counter 0 Interrupt Mask Register
- 11.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register
- 12. 16-bit Timer/Counter1
- 12.1 Features
- 12.2 Overview
- 12.3 Timer/Counter Clock Sources
- 12.4 Counter Unit
- 12.5 Input Capture Unit
- 12.6 Output Compare Units
- 12.7 Compare Match Output Unit
- 12.8 Modes of Operation
- 12.9 Timer/Counter Timing Diagrams
- 12.10 Accessing 16-bit Registers
- 12.11 Register Description
- 12.11.1 TCCR1A – Timer/Counter1 Control Register A
- 12.11.2 TCCR1B – Timer/Counter1 Control Register B
- 12.11.3 TCCR1C – Timer/Counter1 Control Register C
- 12.11.4 TCNT1H and TCNT1L – Timer/Counter1
- 12.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A
- 12.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B
- 12.11.7 ICR1H and ICR1L – Input Capture Register 1
- 12.11.8 TIMSK1 – Timer/Counter Interrupt Mask Register 1
- 12.11.9 TIFR1 – Timer/Counter Interrupt Flag Register 1
- 13. Timer/Counter Prescaler
- 14. USI – Universal Serial Interface
- 15. Analog Comparator
- 16. Analog to Digital Converter
- 16.1 Features
- 16.2 Overview
- 16.3 Operation
- 16.4 Starting a Conversion
- 16.5 Prescaling and Conversion Timing
- 16.6 Changing Channel or Reference Selection
- 16.7 ADC Noise Canceler
- 16.8 Analog Input Circuitry
- 16.9 Noise Canceling Techniques
- 16.10 ADC Accuracy Definitions
- 16.11 ADC Conversion Result
- 16.12 Temperature Measurement
- 16.13 Register Description
- 17. debugWIRE On-chip Debug System
- 18. Self-Programming the Flash
- 18.1 Performing Page Erase by SPM
- 18.2 Filling the Temporary Buffer (Page Loading)
- 18.3 Performing a Page Write
- 18.4 Addressing the Flash During Self-Programming
- 18.5 EEPROM Write Prevents Writing to SPMCSR
- 18.6 Reading Lock, Fuse and Signature Data from Software
- 18.7 Preventing Flash Corruption
- 18.8 Programming Time for Flash when Using SPM
- 18.9 Register Description
- 19. Memory Programming
- 19.1 Program And Data Memory Lock Bits
- 19.2 Fuse Bytes
- 19.3 Device Signature Imprint Table
- 19.4 Page Size
- 19.5 Serial Programming
- 19.6 High-voltage Serial Programming
- 19.7 High-Voltage Serial Programming Algorithm
- 19.7.1 Enter High-voltage Serial Programming Mode
- 19.7.2 Considerations for Efficient Programming
- 19.7.3 Chip Erase
- 19.7.4 Programming the Flash
- 19.7.5 Programming the EEPROM
- 19.7.6 Reading the Flash
- 19.7.7 Reading the EEPROM
- 19.7.8 Programming and Reading the Fuse and Lock Bits
- 19.7.9 Reading the Signature Bytes and Calibration Byte
- 19.7.10 Power-off sequence
- 20. Electrical Characteristics
- 21. Typical Characteristics
- 21.1 Supply Current of I/O Modules
- 21.2 Active Supply Current
- 21.3 Idle Supply Current
- 21.4 Power-down Supply Current
- 21.5 Standby Supply Current
- 21.6 Pin Pull-up
- 21.7 Pin Driver Strength
- 21.8 Pin Threshold and Hysteresis
- 21.9 BOD Threshold and Analog Comparator Offset
- 21.10 Internal Oscillator Speed
- 21.11 Current Consumption of Peripheral Units
- 21.12 Current Consumption in Reset and Reset Pulsewidth
- 22. Register Summary
- 23. Instruction Set Summary
- 24. Ordering Information
- 25. Packaging Information
- 26. Errata
- 27. Datasheet Revision History
- Table of Contents
160
8006K–AVR–10/10
ATtiny24/44/84
19.2 Fuse Bytes
The ATtiny24/44/84 have three fuse bytes. Table 19-3, Table 19-4 and Table 19-5 briefly
describe the functionality of all the fuses and how they are mapped into the fuse bytes. Note that
the fuses are read as logical zero, “0”, if they are programmed.
Notes: 1. Enables SPM instruction. See “Self-Programming the Flash” on page 153.
Notes: 1. See “Alternate Functions of Port B” on page 65 for description of RSTDISBL and DWEN
Fuses. After programming the RSTDISBL fuse, high-voltage serial programming must be used
to change fuses and allow further programming.
2. DWEN must be unprogrammed when Lock Bit security is required. See “Program And Data
Memory Lock Bits” on page 159.
3. The SPIEN Fuse is not accessible in SPI programming mode.
4. Programming this fues will disable the Watchdog Timer Interrupt. See “WDT Configuration as
a Function of the Fuse Settings of WDTON” on page 43 for details.
5. See Table 20-7 on page 179 for BODLEVEL Fuse decoding.
Table 19-3. Fuse Extended Byte
Fuse Extended Byte Bit No Description Default Value
7 - 1 (unprogrammed)
6 - 1 (unprogrammed)
5 - 1 (unprogrammed)
4 - 1 (unprogrammed)
3 - 1 (unprogrammed)
2 - 1 (unprogrammed)
1 - 1 (unprogrammed)
SELFPRGEN
(1)
0 Self-Programming Enable 1 (unprogrammed)
Table 19-4. Fuse High Byte
Fuse High Byte Bit No Description Default Value
RSTDISBL
(1)
7 External Reset disable 1 (unprogrammed)
DWEN
(2)
6 DebugWIRE Enable 1 (unprogrammed)
SPIEN
(3)
6
Enable Serial Program and Data
Downloading
0 (programmed, SPI prog.
enabled)
WDTON
(4)
4 Watchdog Timer always on 1 (unprogrammed)
EESAVE 3
EEPROM memory is preserved through
the Chip Erase
1 (unprogrammed,
EEPROM not preserved)
BODLEVEL2
(5)
2 Brown-out Detector trigger level 1 (unprogrammed)
BODLEVEL1
(5)
1 Brown-out Detector trigger level 1 (unprogrammed)
BODLEVEL0
(5)
0 Brown-out Detector trigger level 1 (unprogrammed)