Datasheet
Table Of Contents
- Features
- 1. Pin Configurations
- 2. Overview
- 3. About
- 4. CPU Core
- 5. Memories
- 6. Clock System
- 7. Power Management and Sleep Modes
- 8. System Control and Reset
- 9. Interrupts
- 10. I/O Ports
- 11. 8-bit Timer/Counter0 with PWM
- 11.1 Features
- 11.2 Overview
- 11.3 Clock Sources
- 11.4 Counter Unit
- 11.5 Output Compare Unit
- 11.6 Compare Match Output Unit
- 11.7 Modes of Operation
- 11.8 Timer/Counter Timing Diagrams
- 11.9 Register Description
- 11.9.1 TCCR0A – Timer/Counter Control Register A
- 11.9.2 TCCR0B – Timer/Counter Control Register B
- 11.9.3 TCNT0 – Timer/Counter Register
- 11.9.4 OCR0A – Output Compare Register A
- 11.9.5 OCR0B – Output Compare Register B
- 11.9.6 TIMSK0 – Timer/Counter 0 Interrupt Mask Register
- 11.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register
- 12. 16-bit Timer/Counter1
- 12.1 Features
- 12.2 Overview
- 12.3 Timer/Counter Clock Sources
- 12.4 Counter Unit
- 12.5 Input Capture Unit
- 12.6 Output Compare Units
- 12.7 Compare Match Output Unit
- 12.8 Modes of Operation
- 12.9 Timer/Counter Timing Diagrams
- 12.10 Accessing 16-bit Registers
- 12.11 Register Description
- 12.11.1 TCCR1A – Timer/Counter1 Control Register A
- 12.11.2 TCCR1B – Timer/Counter1 Control Register B
- 12.11.3 TCCR1C – Timer/Counter1 Control Register C
- 12.11.4 TCNT1H and TCNT1L – Timer/Counter1
- 12.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A
- 12.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B
- 12.11.7 ICR1H and ICR1L – Input Capture Register 1
- 12.11.8 TIMSK1 – Timer/Counter Interrupt Mask Register 1
- 12.11.9 TIFR1 – Timer/Counter Interrupt Flag Register 1
- 13. Timer/Counter Prescaler
- 14. USI – Universal Serial Interface
- 15. Analog Comparator
- 16. Analog to Digital Converter
- 16.1 Features
- 16.2 Overview
- 16.3 Operation
- 16.4 Starting a Conversion
- 16.5 Prescaling and Conversion Timing
- 16.6 Changing Channel or Reference Selection
- 16.7 ADC Noise Canceler
- 16.8 Analog Input Circuitry
- 16.9 Noise Canceling Techniques
- 16.10 ADC Accuracy Definitions
- 16.11 ADC Conversion Result
- 16.12 Temperature Measurement
- 16.13 Register Description
- 17. debugWIRE On-chip Debug System
- 18. Self-Programming the Flash
- 18.1 Performing Page Erase by SPM
- 18.2 Filling the Temporary Buffer (Page Loading)
- 18.3 Performing a Page Write
- 18.4 Addressing the Flash During Self-Programming
- 18.5 EEPROM Write Prevents Writing to SPMCSR
- 18.6 Reading Lock, Fuse and Signature Data from Software
- 18.7 Preventing Flash Corruption
- 18.8 Programming Time for Flash when Using SPM
- 18.9 Register Description
- 19. Memory Programming
- 19.1 Program And Data Memory Lock Bits
- 19.2 Fuse Bytes
- 19.3 Device Signature Imprint Table
- 19.4 Page Size
- 19.5 Serial Programming
- 19.6 High-voltage Serial Programming
- 19.7 High-Voltage Serial Programming Algorithm
- 19.7.1 Enter High-voltage Serial Programming Mode
- 19.7.2 Considerations for Efficient Programming
- 19.7.3 Chip Erase
- 19.7.4 Programming the Flash
- 19.7.5 Programming the EEPROM
- 19.7.6 Reading the Flash
- 19.7.7 Reading the EEPROM
- 19.7.8 Programming and Reading the Fuse and Lock Bits
- 19.7.9 Reading the Signature Bytes and Calibration Byte
- 19.7.10 Power-off sequence
- 20. Electrical Characteristics
- 21. Typical Characteristics
- 21.1 Supply Current of I/O Modules
- 21.2 Active Supply Current
- 21.3 Idle Supply Current
- 21.4 Power-down Supply Current
- 21.5 Standby Supply Current
- 21.6 Pin Pull-up
- 21.7 Pin Driver Strength
- 21.8 Pin Threshold and Hysteresis
- 21.9 BOD Threshold and Analog Comparator Offset
- 21.10 Internal Oscillator Speed
- 21.11 Current Consumption of Peripheral Units
- 21.12 Current Consumption in Reset and Reset Pulsewidth
- 22. Register Summary
- 23. Instruction Set Summary
- 24. Ordering Information
- 25. Packaging Information
- 26. Errata
- 27. Datasheet Revision History
- Table of Contents
127
8006K–AVR–10/10
ATtiny24/44/84
Note: 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively
to avoid confusion between the modes of operation.
• Bits 3:2 – USICS1, USICS0: Clock Source Select
These bits set the clock source for the USI Data Register and counter. The data output latch
ensures that the output is changed at the opposite edge of the sampling of the data input
(DI/SDA) when using external clock source (USCK/SCL). When software strobe or
Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and
therefore the output is changed immediately.
Clearing the USICS1:0 bits enables software strobe option. When using this option, writing a
one to the USICLK bit clocks both the USI Data Register and the counter. For external clock
source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external
clocking and software clocking by the USITC strobe bit.
Table 14-1. Relationship between USIWM1:0 and USI Operation
USIWM1 USIWM0 Description
00
Outputs, clock hold, and start detector disabled.
Port pins operate as normal.
01
Three-wire mode. Uses DO, DI, and USCK pins.
The Data Output (DO) pin overrides the corresponding bit in the PORTA
register. However, the corresponding DDRA bit still controls the data direction.
When the port pin is set as input the pin pull-up is controlled by the PORTA bit.
The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal port
operation. When operating as master, clock pulses are software generated by
toggling the PORTA register, while the data direction is set to output. The
USITC bit in the USICR Register can be used for this purpose.
10
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins
(1)
.
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and
use open-collector output drives. The output drivers are enabled by setting the
corresponding bit for SDA and SCL in the DDRA register.
When the output driver is enabled for the SDA pin, the output driver will force the
line SDA low if the output of the
USI Data Register or the corresponding bit in
the PORTA register is zero. Otherwise, the SDA line will not be driven (i.e., it is
released). When the SCL pin output driver is enabled the SCL line will be forced
low if the corresponding bit in the PORTA register is zero, or by the start
detector. Otherwise the SCL line will not be driven.
The SCL line is held low when a start detector detects a start condition and the
output is enabled. Clearing the Start Condition Flag (USISIF) releases the line.
The SDA and SCL pin inputs is not affected by enabling this mode. Pull-ups on
the SDA and SCL port pin are disabled in Two-wire mode.
11
Two-wire mode. Uses SDA and SCL pins.
Same operation as in two-wire mode above, except that the SCL line is also
held low when a counter overflow occurs, and until the Counter Overflow Flag
(USIOIF) is cleared.