Datasheet
Table Of Contents
- Features
- 1. Pin Configurations
- 2. Overview
- 3. About
- 4. CPU Core
- 5. Memories
- 6. Clock System
- 7. Power Management and Sleep Modes
- 8. System Control and Reset
- 9. Interrupts
- 10. I/O Ports
- 11. 8-bit Timer/Counter0 with PWM
- 11.1 Features
- 11.2 Overview
- 11.3 Clock Sources
- 11.4 Counter Unit
- 11.5 Output Compare Unit
- 11.6 Compare Match Output Unit
- 11.7 Modes of Operation
- 11.8 Timer/Counter Timing Diagrams
- 11.9 Register Description
- 11.9.1 TCCR0A – Timer/Counter Control Register A
- 11.9.2 TCCR0B – Timer/Counter Control Register B
- 11.9.3 TCNT0 – Timer/Counter Register
- 11.9.4 OCR0A – Output Compare Register A
- 11.9.5 OCR0B – Output Compare Register B
- 11.9.6 TIMSK0 – Timer/Counter 0 Interrupt Mask Register
- 11.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register
- 12. 16-bit Timer/Counter1
- 12.1 Features
- 12.2 Overview
- 12.3 Timer/Counter Clock Sources
- 12.4 Counter Unit
- 12.5 Input Capture Unit
- 12.6 Output Compare Units
- 12.7 Compare Match Output Unit
- 12.8 Modes of Operation
- 12.9 Timer/Counter Timing Diagrams
- 12.10 Accessing 16-bit Registers
- 12.11 Register Description
- 12.11.1 TCCR1A – Timer/Counter1 Control Register A
- 12.11.2 TCCR1B – Timer/Counter1 Control Register B
- 12.11.3 TCCR1C – Timer/Counter1 Control Register C
- 12.11.4 TCNT1H and TCNT1L – Timer/Counter1
- 12.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A
- 12.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B
- 12.11.7 ICR1H and ICR1L – Input Capture Register 1
- 12.11.8 TIMSK1 – Timer/Counter Interrupt Mask Register 1
- 12.11.9 TIFR1 – Timer/Counter Interrupt Flag Register 1
- 13. Timer/Counter Prescaler
- 14. USI – Universal Serial Interface
- 15. Analog Comparator
- 16. Analog to Digital Converter
- 16.1 Features
- 16.2 Overview
- 16.3 Operation
- 16.4 Starting a Conversion
- 16.5 Prescaling and Conversion Timing
- 16.6 Changing Channel or Reference Selection
- 16.7 ADC Noise Canceler
- 16.8 Analog Input Circuitry
- 16.9 Noise Canceling Techniques
- 16.10 ADC Accuracy Definitions
- 16.11 ADC Conversion Result
- 16.12 Temperature Measurement
- 16.13 Register Description
- 17. debugWIRE On-chip Debug System
- 18. Self-Programming the Flash
- 18.1 Performing Page Erase by SPM
- 18.2 Filling the Temporary Buffer (Page Loading)
- 18.3 Performing a Page Write
- 18.4 Addressing the Flash During Self-Programming
- 18.5 EEPROM Write Prevents Writing to SPMCSR
- 18.6 Reading Lock, Fuse and Signature Data from Software
- 18.7 Preventing Flash Corruption
- 18.8 Programming Time for Flash when Using SPM
- 18.9 Register Description
- 19. Memory Programming
- 19.1 Program And Data Memory Lock Bits
- 19.2 Fuse Bytes
- 19.3 Device Signature Imprint Table
- 19.4 Page Size
- 19.5 Serial Programming
- 19.6 High-voltage Serial Programming
- 19.7 High-Voltage Serial Programming Algorithm
- 19.7.1 Enter High-voltage Serial Programming Mode
- 19.7.2 Considerations for Efficient Programming
- 19.7.3 Chip Erase
- 19.7.4 Programming the Flash
- 19.7.5 Programming the EEPROM
- 19.7.6 Reading the Flash
- 19.7.7 Reading the EEPROM
- 19.7.8 Programming and Reading the Fuse and Lock Bits
- 19.7.9 Reading the Signature Bytes and Calibration Byte
- 19.7.10 Power-off sequence
- 20. Electrical Characteristics
- 21. Typical Characteristics
- 21.1 Supply Current of I/O Modules
- 21.2 Active Supply Current
- 21.3 Idle Supply Current
- 21.4 Power-down Supply Current
- 21.5 Standby Supply Current
- 21.6 Pin Pull-up
- 21.7 Pin Driver Strength
- 21.8 Pin Threshold and Hysteresis
- 21.9 BOD Threshold and Analog Comparator Offset
- 21.10 Internal Oscillator Speed
- 21.11 Current Consumption of Peripheral Units
- 21.12 Current Consumption in Reset and Reset Pulsewidth
- 22. Register Summary
- 23. Instruction Set Summary
- 24. Ordering Information
- 25. Packaging Information
- 26. Errata
- 27. Datasheet Revision History
- Table of Contents
126
8006K–AVR–10/10
ATtiny24/44/84
The 4-bit counter increments by one for each clock generated either by the external clock edge
detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe
bits. The clock source depends on the setting of the USICS1:0 bits.
For external clock operation a special feature is added that allows the clock to be generated by
writing to the USITC strobe bit. This feature is enabled by choosing an external clock source
(USICS1 = 1) and writing a one to the USICLK bit.
Note that even when no wire mode is selected (USIWM1:0 = 0) the external clock input
(USCK/SCL) can still be used by the counter.
14.5.4 USICR – USI Control Register
The USI Control Register includes bits for interrupt enable, setting the wire mode, selecting the
clock and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the start condition detector interrupt. If there is a pending interrupt
and USISIE and the Global Interrupt Enable Flag are set to one the interrupt will be executed
immediately. Refer to the USISIF bit description on page 125 for further details.
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the counter overflow interrupt. If there is a pending interrupt and
USIOIE and the Global Interrupt Enable Flag are set to one the interrupt will be executed imme-
diately. Refer to the USIOIF bit description on page 125 for further details.
• Bits 5:4 – USIWM1, USIWM0: Wire Mode
These bits set the type of wire mode to be used, as shown in Table 14-1 on page 127.
Basically, only the function of the outputs are affected by these bits. Data and clock inputs are
not affected by the mode selected and will always have the same function. The counter and USI
Data Register can therefore be clocked externally and data input sampled, even when outputs
are disabled.
Bit 7 6 5 4 3 2 1 0
0x0D (0x2D) USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC USICR
Read/Write R/W R/W R/W R/W R/W R/W W W
Initial Value 0 0 0 0 0 0 0 0