Datasheet

87
8246A–AVR–11/09
ATtiny2313A/4313
The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 11-8, “Waveform
Generation Mode Bit Description” on page 83.
• Bit 0 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data
in OCR0A – Output Compare Register0 A. OCF0A is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),
and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.