Datasheet

86
8246A–AVR–11/09
ATtiny2313A/4313
11.9.6 TIMSK – Timer/Counter Interrupt Mask Register
• Bit 4 – Res: Reserved Bit
This bit is reserved bit in the ATtiny2313A/4313 and will always read as zero.
• Bit 2 – OCIE0B: Timer/Counter0 Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter
Interrupt Flag Register – TIFR.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-
rupt Flag Register – TIFR.
• Bit 0 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR.
11.9.7 TIFR – Timer/Counter Interrupt Flag Register
• Bit 4 – Res: Reserved Bit
This bit is reserved bit in the ATtiny2313A/4313 and will always read as zero.
• Bit 2 – OCF0B: Output Compare Flag 0 B
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in
OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),
and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by
writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt
Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
Bit 76543210
0x39 (0x59)
TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A TIMSK
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x38 (0x58)
TOV1 OCF1A OCF1B – ICF1 OCF0B TOV0 OCF0A TIFR
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value00000000