Datasheet

68
8246A–AVR–11/09
ATtiny2313A/4313
10.3 Register Description
10.3.1 MCUCR – MCU Control Register
• Bit 7 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-
figuring the Pin” on page 55 for more details about this feature.
10.3.2 PORTA – Port A Data Register
10.3.3 DDRA – Port A Data Direction Register
Table 10-10. Overriding Signals for Alternate Functions in PD3..PD0
Signal
Name
PD3/INT1/
PCINT14
PD2/INT0/XCK/CKOUT/
PCINT13
PD1/TXD/
PCINT12 PD0/RXD/PCINT11
PUOE 0 0 TXD_OE RXD_OE
PUOV 0 0 0 PORTD0 • PUD
DDOE 0 0 TXD_OE RXD_EN
DDOV 0 0 1 0
PVOE 0 XCKO_PVOE TXD_OE 0
PVOV 0 XCKO_PVOV TXD_PVOV 0
PTOE 0 0 0 0
DIEOE
INT1 Enable +
PCINT14
INT0 Enable/
XCK Input Enable/PCINT13
PCINT12 PCINT11
DIEOV PCINT14 PCINT13 PCINT12 PCINT11
DI
INT1 Input/
PCINT14
INT0 Input/XCK Input/
PCINT13
PCINT12 RXD Input/PCINT11
AIO – – – –
Bit 7 6 5 4 3 2 1 0
0x35 (0x55) PUD
SM1 SE SM0 ISC11 ISC10 ISC01 ISC00 MCUCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x1B (0x3B)
–––––PORTA2PORTA1PORTA0
PORTA
Read/Write RRRRRR/WR/WR/W
Initial Value00000000
Bit 76543210
0x1A (0x3A)
–––––
DDA2 DDA1 DDA0 DDRA
Read/Write RRRRRR/WR/WR/W
Initial Value00000000