Datasheet

8246A–AVR–11/09

ATtiny2313A/4313

The most typical and general setup for the Interrupt Vector Addresses in ATtiny2313A/4313

shown below:

Address Labels Code Comments

0x0000 rjmp RESET ; Reset Handler

0x0001 rjmp INT0 ; External Interrupt0 Handler

0x0002 rjmp INT1 ; External Interrupt1 Handler

0x0003 rjmp TIM1_CAPT ; Timer1 Capture Handler

0x0004 rjmp TIM1_COMPA ; Timer1 CompareA Handler

0x0005 rjmp TIM1_OVF ; Timer1 Overflow Handler

0x0006 rjmp TIM0_OVF ; Timer0 Overflow Handler

0x0007 rjmp USART0_RXC ; USART0 RX Complete Handler

0x0008 rjmp USART0_DRE ; USART0,UDR Empty Handler

0x0009 rjmp USART0_TXC ; USART0 TX Complete Handler

0x000A rjmp ANA_COMP ; Analog Comparator Handler

0x000B rjmp PCINT0 ; PCINT0 Handler

0x000C rjmp TIMER1_COMPB ; Timer1 Compare B Handler

0x000D rjmp TIMER0_COMPA ; Timer0 Compare A Handler

0x000E rjmp TIMER0_COMPB ; Timer0 Compare B Handler

0x000F rjmp USI_START ; USI Start Handler

0x0010 rjmp USI_OVERFLOW ; USI Overflow Handler

0x0011 rjmp EE_READY ; EEPROM Ready Handler

0x0012 rjmp WDT_OVERFLOW ; Watchdog Overflow Handler

0x0013 rjmp PCINT1 ; PCINT1 Handler

0x0014 rjmp PCINT2 ; PCINT2 Handler

;

0x0013 RESET: ldi r16, low(RAMEND); Main program start

0x0014 out SPL,r16 Set Stack Pointer to top of RAM

0x0015 sei ; Enable interrupts

0x0016 <instr> xxx

... ... ... ...

9.2 External Interrupts

External Interrupts are triggered by the INT0 or INT1 pin or any of the PCINT17..0 pins. Observe

that, if enabled, the interrupts will trigger even if the INT0, INT1 or PCINT17..0 pins are config-

ured as outputs. This feature provides a way of generating a software interrupt. Pin change 0

interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles. Pin change 1 interrupts PCI1

will trigger if any enabled PCINT10..8 pin toggles. Pin change 2 interrupts PCI2 will trigger, if any

enabled PCINT17..11 pin toggles. The PCMSK0, PCMSK1, and PCMSK2 Registers control

which pins contribute to the pin change interrupts. Pin change interrupts on PCINT17..0 are

detected asynchronously, which means that these interrupts can be used for waking the part

also from sleep modes other than Idle mode.

The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is

set up as shown in “MCUCR – MCU Control Register” on page 50. When the INT0 or INT1 inter-

rupt is enabled and configured as level triggered, the interrupt will trigger as long as the pin is

held low. Note that recognition of falling or rising edge interrupts on INT0 or INT1 requires the

presence of an I/O clock, as described in “Clock Sources” on page 25.