Datasheet

8246A–AVR–11/09

ATtiny2313A/4313

8.2.4 Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period t

TOUT

. See

“Interrupts” on page 47 for details on operation of the Watchdog Timer.

Figure 8-6. Watchdog Reset During Operation

8.3 Internal Voltage Reference

ATtiny2313A/4313 features an internal bandgap reference. This reference is used for Brown-out

Detection, and it can be used as an input to the Analog Comparator. The bandgap voltage varies

with supply voltage and temperature.

8.3.1 Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The

start-up time is given in “System and Reset Characteristics” on page 198. To save power, the

reference is not always turned on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).

2. When the internal reference is connected to the Analog Comparator (by setting the

ACBG bit in ACSR).

Thus, when the BOD is not enabled, after setting the ACBG bit, the user must always allow the

reference to start up before the output from the Analog Comparator. To reduce power consump-

tion in Power-down mode, the user can avoid the three conditions above to ensure that the

reference is turned off before entering Power-down mode.

8.4 Watchdog Timer

The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling

the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table

8-3 on page 46. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The

Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different

clock cycle periods can be selected to determine the reset period. If the reset period expires

without another Watchdog Reset, the ATtiny2313A/4313 resets and executes from the Reset

Vector. For timing details on the Watchdog Reset, refer to Table 8-3 on page 46.