Datasheet

36
8246A–AVR–11/09
ATtiny2313A/4313
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
CC
/2 on an input pin can cause significant current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Register (DIDR). See “DIDR
– Digital Input Disable Register” on page 168 for details.
7.5 Register Description
7.5.1 MCUCR – MCU Control Register
The Sleep Mode Control Register contains control bits for power management.
• Bits 6, 4 – SM1..0: Sleep Mode Select Bits 1 and 0
These bits select between the four available sleep modes as shown in Table 7-2.
Note: Standby mode is only recommended for use with external crystals or resonators.
• Bit 5 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
7.5.2 PRR – Power Reduction Register
The Power Reduction Register provides a method to reduce power consumption by allowing
peripheral clock signals to be disabled.
• Bits 7..4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 3 – PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1
is enabled, operation will continue like before the shutdown.
Bit 76543210
0x35 (0x55)
PUD SM1 SE SM0 ISC11 ISC10 ISC01 ISC00 MCUCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Table 7-2. Sleep Mode Select
SM1 SM0 Sleep Mode
00Idle
0 1 Power-down
1 0 Standby
1 1 Power-down
Bit 7654 3 2 1 0
0x06 (0x26) – – – – PRTIM1 PRTIM0 PRUSI PRUSART PRR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0