Datasheet

33
8246A–AVR–11/09
ATtiny2313A/4313
7. Power Management and Sleep Modes
The high performance and industry leading code efficiency makes the AVR microcontrollers an
ideal choise for low power applications. In addition, sleep modes enable the application to shut
down unused modules in the MCU, thereby saving power. The AVR provides various sleep
modes allowing the user to tailor the power consumption to the application’s requirements.
7.1 Sleep Modes
Figure 6-1 on page 24 presents the different clock systems and their distribution in
ATtiny2313A/4313. The figure is helpful in selecting an appropriate sleep mode. Table 7-1
shows the different sleep modes and their wake up sources.
Note: 1. For INT0 and INT1, only level interrupt.
To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a
SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Register select which
sleep mode (Idle, Standby or Power-down) will be activated by the SLEEP instruction. See
Table 7-2 on page 36 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
Note that if a level triggered interrupt is used for wake-up the changed level must be held for
some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See
“External Interrupts” on page 48 for details.
7.1.1 Idle Mode
When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing Analog Comparator, USI, Timer/Counter, Watchdog, and the
interrupt system to continue operating. This sleep mode basically halts clk
CPU
and clk
FLASH
, while
allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,
the Analog Comparator can be powered down by setting the ACD bit in “ACSR – Analog Com-
Table 7-1. Active Clock Domains and Wake-up Sources in Different Sleep Modes
Sleep Mode
Active Clock
Domains Oscillators Wake-up Sources
clk
CPU
clk
FLASH
clk
IO
Main Clock Source Enabled INT0, INT1 and Pin Change USI Start Condition SPM/EEPROM Ready Interrupt Other I/O Watchdog Interrupt
Idle X X XXXXX
Power-down X
(1)
XX
Stand-by X X
(1)
XX