Datasheet

29
8246A–AVR–11/09
ATtiny2313A/4313
Notes: 1. These options should only be used when not operating close to the maximum frequency of the
device, and only if frequency stability at start-up is not important for the application. These
options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability
at start-up. They can also be used with crystals when not operating close to the maximum fre-
quency of the device, and if frequency stability at start-up is not important for the application.
6.3 System Clock Prescaler
The ATtiny2313A/4313 has a system clock prescaler, and the system clock can be divided by
setting the “CLKPR – Clock Prescale Register” on page 30. This feature can be used to
decrease the system clock frequency and the power consumption when the requirement for pro-
cessing power is low. This can be used with all clock source options, and it will affect the clock
frequency of the CPU and all synchronous peripherals. clk
I/O
, clk
CPU
, and clk
FLASH
are divided by
a factor as shown in Table 6-8 on page 30.
6.3.1 Switching Time
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the
state of the prescaler - even if it were readable, and the exact time it takes to switch from one
clock division to the other cannot be exactly predicted. From the time the CLKPS values are writ-
ten, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this
interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is
the period corresponding to the new prescaler setting.
Table 6-7. Start-up Times for the Crystal Oscillator Clock Selection
CKSEL0 SUT1..0
Start-up Time from
Power-down and
Power-save
Additional Delay
from Reset
(V
CC
= 5.0V) Recommended Usage
0 00 258 CK
(1)
14CK + 4 ms
Ceramic resonator, fast
rising power
0 01 258 CK
(1)
14CK + 64 ms
Ceramic resonator,
slowly rising power
010 1K CK
(2)
14CK
Ceramic resonator,
BOD enabled
011 1K CK
(2)
14CK + 4 ms
Ceramic resonator, fast
rising power
100 1K CK
(2)
14CK + 64 ms
Ceramic resonator,
slowly rising power
1 01 16K CK 14CK
Crystal Oscillator, BOD
enabled
1 10 16K CK 14CK + 4 ms
Crystal Oscillator, fast
rising power
1 11 16K CK 14CK + 64 ms
Crystal Oscillator,
slowly rising power