Datasheet

192
8246A–AVR–11/09
ATtiny2313A/4313
next page (See Table 20-14 on page 192). In a chip erased device, no 0xFF in the data
file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the
content at the selected address at serial output MISO.
7. At the end of the programming session, RESET
can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET
to “1”.
Turn V
CC
power off.
Table 20-14. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay
t
WD_FLASH
4.5 ms
t
WD_EEPROM
4.0 ms
t
WD_ERASE
9.0 ms
t
WD_FUSE
4.5 ms