Datasheet

182
8246A–AVR–11/09
ATtiny2313A/4313
20.5 Parallel Programming Parameters, Pin Mapping, and Commands
This section describes how to parallel program and verify Flash Program memory, EEPROM
Data memory, Memory Lock bits, and Fuse bits in the ATtiny2313A/4313. Pulses are assumed
to be at least 250 ns unless otherwise noted.
20.5.1 Signal Names
In this section, some pins of the ATtiny2313A/4313 are referenced by signal names describing
their functionality during parallel programming, see Figure 20-1 and Table 20-9 on page 182.
Pins not described in the following table are referenced by pin names.
Figure 20-1. Parallel Programming
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.
The bit coding is shown in Table 20-11 on page 183.
Table 20-9. Pin Name Mapping
Signal Name in
Programming
Mode
Pin
Name I/O Function
RDY/BSY
PD1 O
0: Device is busy programming,
1: Device is ready for new command.
OE
PD2 I Output Enable (Active low).
WR
PD3 I Write Pulse (Active low).
BS1/PAGEL PD4 I
Byte Select 1 (“0” selects low byte, “1” selects high byte).
Program Memory and EEPROM Data Page Load.
XA0 PD5 I XTAL Action Bit 0
XA1/BS2 PD6 I
XTAL Action Bit 1.
Byte Select 2 (“0” selects low byte, “1” selects 2’nd high
byte).
DATA I/O PB7-0 I/O Bi-directional Data bus (Output when OE
is low).
VCC
+5V
GND
XTAL1
PD1
PD2
PD3
PD4
PD5
PD6
PB7 - PB0 DATA I/O
RESET
+12 V
BS1/PAGEL
XA0
XA1/BS2
OE
RDY/BSY
WR