Datasheet

17
8246A–AVR–11/09
ATtiny2313A/4313
Figure 5-3. On-chip Data SRAM Access Cycles
5.3 EEPROM Data Memory
The ATtiny2313A/4313 contains 128/256 bytes of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register. For a detailed description of Serial data
downloading to the EEPROM, see page 190.
5.3.1 EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access times for the EEPROM are given in Table 5-1 on page 22. A self-timing func-
tion, however, lets the user software detect when the next byte can be written. If the user code
contains instructions that write the EEPROM, some precautions must be taken. In heavily fil-
tered power supplies, V
CC
is likely to rise or fall slowly on Power-up/down. This causes the
device for some period of time to run at a voltage lower than specified as minimum for the clock
frequency used. See “Preventing EEPROM Corruption” on page 20 for details on how to avoid
problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to “Atomic Byte Programming” on page 17 and “Split Byte Programming” on page 18 for
details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
5.3.2 Atomic Byte Programming
Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the
user must write the address into the EEARL Register and data into EEDR Register. If the
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction