Datasheet

154
8246A–AVR–11/09
ATtiny2313A/4313
• Bit 5:3 – Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRC is written.
• Bit 2 – UDORD: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the
data word is transmitted first. Refer to the Frame Formats section page 4 for details.
• Bit 1 – UCPHA: Clock Phase
The UCPHA bit setting determine if data is sampled on the leasing edge (first) or tailing (last)
edge of XCK. Refer to the SPI Data Modes and Timing section page 4 for details.
• Bit 0 – UCPOL: Clock Polarity
The UCPOL bit sets the polarity of the XCK clock. The combination of the UCPOL and UCPHA
bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and Timing
section page 4 for details.
15.8.5 UBRRL and UBRRH – USART MSPIM Baud Rate Registers
The function and bit description of the baud rate registers in MSPI mode is identical to normal
USART operation. See “UBRRL and UBRRH – USART Baud Rate Registers” on page 140.