Datasheet

153
8246A–AVR–11/09
ATtiny2313A/4313
• Bit 6 – TXCIE: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC Flag. A USART Transmit Complete interrupt
will be generated only if the TXCIE bit is written to one, the Global Interrupt Flag in SREG is writ-
ten to one and the TXC bit in UCSRA is set.
• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDRE Flag. A Data Register Empty interrupt will
be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written
to one and the UDRE bit in UCSRA is set.
• Bit 4 – RXEN: Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override
normal port operation for the RxD pin when enabled. Disabling the Receiver will flush the receive
buffer. Only enabling the receiver in MSPI mode (i.e. setting RXEN=1 and TXEN=0) has no
meaning since it is the transmitter that controls the transfer clock and since only master mode is
supported.
• Bit 3 – TXEN: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXEN to zero)
will not become effective until ongoing and pending transmissions are completed, i.e., when the
Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted.
When disabled, the Transmitter will no longer override the TxD port.
• Bit 2:0 – Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRB is written.
15.8.4 UCSRC – USART MSPIM Control and Status Register C
• Bit 7:6 – UMSEL1:0: USART Mode Select
These bits select the mode of operation of the USART as shown in Table 15-4. See “UCSRC –
USART Control and Status Register C” on page 139 for full description of the normal USART
operation. The MSPIM is enabled when both UMSEL bits are set to one. The UDORD, UCPHA,
and UCPOL can be set in the same write operation where the MSPIM is enabled.
Bit 7 6 5 4 3 2 1 0
0x03 (0x23) UMSEL1 UMSEL0 - - - UDORD UCPHA UCPOL UCSRC
Read/Write R/W R/W R R R R/W R/W R/W
Initial Value 0 0 0 0 0 1 1 0
Table 15-4. UMSEL Bits Settings
UMSEL1 UMSEL0 Mode
0 0 Asynchronous USART
0 1 Synchronous USART
1 0 Reserved
1 1 Master SPI (MSPIM)