Datasheet

146
8246A–AVR–11/09
ATtiny2313A/4313
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD Baud rate (in bits per second, bps)
f
OSC
System Oscillator clock frequency
UBRR Contents of the UBRRH and UBRRL Registers, (0-4095)
15.4 SPI Data Modes and Timing
There are four combinations of XCK (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHA and UCPOL. The data transfer timing diagrams are
shown in Figure 15-1. Data bits are shifted out and latched in on opposite edges of the XCK sig-
nal, ensuring sufficient time for data signals to stabilize. The UCPOL and UCPHA functionality is
summarized in Table 15-2. Note that changing the setting of any of these bits will corrupt all
ongoing communication for both the Receiver and Transmitter.
Figure 15-1. UCPHA and UCPOL data transfer timing diagrams.
Table 15-1. Equations for Calculating Baud Rate Register Setting
Operating Mode
Equation for Calculating Baud
Rate
(1)
Equation for Calculating UBRRn
Value
Synchronous Master
mode
BAUD
f
OSC
2 UBRR 1+()
-----------------------------------=
UBRR
f
OSC
2BAUD
-------------------- 1–=
Table 15-2. UCPOL and UCPHA Functionality-
UCPOL UCPHA SPI Mode Leading Edge Trailing Edge
0 0 0 Sample (Rising) Setup (Falling)
0 1 1 Setup (Rising) Sample (Falling)
1 0 2 Sample (Falling) Setup (Rising)
1 1 3 Setup (Falling) Sample (Rising)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
UCPOL=0 UCPOL=1
UCPHA=0
UCPHA=1