Datasheet

140
8246A–AVR–11/09
ATtiny2313A/4313
• Bit 3 – USBS: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
• Bit 2:1 – UCSZ1:0: Character Size
The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Char-
acter SiZe) in a frame the Receiver and Transmitter use. See Table 14-7.
• Bit 0 – UCPOL: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOL bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCK).
14.10.5 UBRRL and UBRRH – USART Baud Rate Registers
Table 14-6. USBS Bit Settings
USBS Stop Bit(s)
01-bit
12-bit
Table 14-7. UCSZ Bits Settings
UCSZ2 UCSZ1 UCSZ0 Character Size
0005-bit
0016-bit
0107-bit
0118-bit
100Reserved
101Reserved
110Reserved
1119-bit
Table 14-8. UCPOL Bit Settings
UCPOL
Transmitted Data Changed (Output of
TxD Pin)
Received Data Sampled (Input on
RxD Pin)
0 Rising XCK Edge Falling XCK Edge
1 Falling XCK Edge Rising XCK Edge
Bit 151413121110 9 8
0x02 (0x22) – – – – UBRR[11:8] UBRRH
0x09 (0x29) UBRR[7:0] UBRRL
Bit 76543210
Read/Write R R R R R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
00000000