Datasheet

139
8246A–AVR–11/09
ATtiny2313A/4313
• Bit 2 – UCSZ2: Character Size
The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Char-
acter SiZe) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8: Receive Data Bit 8
RXB8 is the ninth data bit of the received character when operating with serial frames with nine
data bits. Must be read before reading the low bits from UDR.
• Bit 0 – TXB8: Transmit Data Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDR.
14.10.4 UCSRC – USART Control and Status Register C
• Bits 7:6 – UMSEL1:0: USART Mode Select
These bits select the mode of operation of the USART as shown in Table 14-4.
Note: 1. For full description of the Master SPI Mode (MSPIM) Operation, see “USART in SPI Mode”
on page 145.
• Bits 5:4 – UPM1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting.
If a mismatch is detected, the UPE Flag in UCSRA will be set.
Bit 7 6 543210
0x03 (0x23) UMSEL1 UMSEL0 UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL UCSRC
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value0 0 000110
Table 14-4. UMSEL Bit Settings
UMSEL1 UMSEL0 Mode
0 0 Asynchronous USART
0 1 Synchronous USART
10Reserved
1 1 Master SPI (MSPIM)
(1)
Table 14-5. UPM Bits Settings
UPM1 UPM0 Parity Mode
00Disabled
01Reserved
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity